| 1565 | -- | 1578 | Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Yunheung Paek. A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures |
| 1579 | -- | 1592 | Cheng Jia, Linda Milor. A DLL Design for Testing I/O Setup and Hold Times |
| 1593 | -- | 1601 | Zhengtao Yu 0002, Xun Liu. Implementing Multiphase Resonant Clocking on a Finite-Impulse Response Filter |
| 1602 | -- | 1615 | Jiangli Zhu, Xinmiao Zhang, Zhongfeng Wang. Backward Interpolation Architecture for Algebraic Soft-Decision Reed-Solomon Decoding |
| 1616 | -- | 1625 | Ming-Fu Sun, Ta-Yang Juan, Kan-Si Lin, Terng-Yin Hsu. Adaptive Frequency-Domain Channel Estimator in 4 , times , 4 MIMO-OFDM Modems |
| 1626 | -- | 1639 | Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer. Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NOC Interconnects |
| 1640 | -- | 1649 | Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori. A Framework for Power-Gating Functional Units in Embedded Microprocessors |
| 1650 | -- | 1654 | Simone Corbetta, Massimo Morandi, Marco Novati, Marco D. Santambrogio, Donatella Sciuto, Paola Spoletini. Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration |
| 1654 | -- | 1659 | Davide Appello, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda. Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs |
| 1659 | -- | 1663 | Lih-Yih Chiou, Shien-Chun Luo. Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics |