| 1369 | -- | 1382 | Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Seok-Hoon Kim, Lee-Sup Kim. A 186-Mvertices/s 161-mW Floating-Point Vertex Processor With Optimized Datapath and Vertex Caches |
| 1383 | -- | 1391 | Amir Zjajo, José Pineda de Gyvez. Analog Automatic Test Pattern Generation for Quasi-Static Structural Test |
| 1392 | -- | 1404 | Ozgur Sinanoglu, Sobeeh Almukhaizim. X-Align: Improving the Scan Cell Observability of Response Compactors |
| 1405 | -- | 1418 | Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin. Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits |
| 1419 | -- | 1432 | Aydin O. Balkan, Gang Qu, Uzi Vishkin. Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip Parallelism |
| 1433 | -- | 1446 | Victor Dumitriu, Gul N. Khan. Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs |
| 1447 | -- | 1460 | Maryam Ashouei, Abhijit Chatterjee. Checksum-Based Probabilistic Transient-Error Compensation for Linear Digital Systems |
| 1461 | -- | 1469 | Moo-young Kim, Dongsuk Shin, Hyunsoo Chae, Chulwoo Kim. A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time |
| 1470 | -- | 1480 | Min Chen, Wei Zhao, Frank Liu, Yu Cao. Finite-Point-Based Transistor Model: A New Approach to Fast Circuit Simulation |
| 1481 | -- | 1494 | Mingjie Lin, Abbas El Gamal. A Low-Power Field-Programmable Gate Array Routing Fabric |
| 1495 | -- | 1507 | Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Murli Tirumala. Architecture-Level Thermal Characterization for Multicore Microprocessors |
| 1508 | -- | 1519 | David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat. Interests and Limitations of Technology Scaling for Subthreshold Logic |
| 1520 | -- | 1533 | Sebastian Herbert, Diana Marculescu. Mitigating the Impact of Variability on Chip-Multiprocessor Power and Performance |
| 1534 | -- | 1545 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell. Variable Input Delay CMOS Logic for Low Power Design |
| 1546 | -- | 1550 | Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi. A High-Speed Word Level Finite Field Multiplier in BBF::2:::m::::: Using Redundant Representation |
| 1551 | -- | 1555 | G. Razavipour, Ali Afzali-Kusha, Massoud Pedram. Design and Analysis of Two Low-Power SRAM Cell Structures |
| 1556 | -- | 1559 | Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian. Analysis of Resistive-Open Defects in SRAM Sense Amplifiers |
| 1559 | -- | 1564 | Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin. Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling |