| 733 | -- | 746 | Feng Lu, Kwang-Ting Cheng. SEChecker: A Sequential Equivalence Checking Framework Based on Kth Invariants |
| 747 | -- | 757 | Pramod Kumar Meher. Systolic and Non-Systolic Scalable Modular Designs of Finite Field Multipliers for Reed-Solomon Codec |
| 758 | -- | 769 | Meng-Fan Chang, Shu-Meng Yang. Analysis and Reduction of Supply Noise Fluctuations Induced by Embedded Via-Programming ROM |
| 770 | -- | 780 | Rupak Samanta, Ganesh Venkataraman, Jiang Hu. Clock Buffer Polarity Assignment for Power Noise Reduction |
| 781 | -- | 792 | Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan S. Choi. Circuit-Level Design Approaches for Radiation-Hard Digital Electronics |
| 793 | -- | 802 | Dayu Yang, Foster F. Dai, Weining Ni, Yin Shi, Richard C. Jaeger. Delta-Sigma Modulation for Direct Digital Frequency Synthesis |
| 803 | -- | 814 | Rajarajan Senguttuvan, Soumendu Bhattacharya, Abhijit Chatterjee. Efficient EVM Testing of Wireless OFDM Transceivers Using Null Carriers |
| 815 | -- | 826 | Ozgur Sinanoglu, Philip Schremmer. Scan Chain Hold-Time Violations: Can They be Tolerated? |
| 827 | -- | 837 | Mohammad A. Makhzan, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi. A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment |
| 838 | -- | 843 | Yuan-Chun Lin, Youn-Long Lin. A Two-Result-per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder |
| 843 | -- | 847 | DiaaEldin Khalil, Debjit Sinha, Hai Zhou, Yehea I. Ismail. A Timing-Dependent Power Estimation Framework Considering Coupling |
| 848 | -- | 852 | Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura. Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping |