| 973 | -- | 982 | Shuo Wang, Lei Wang. Exploiting Memory Soft Redundancy for Joint Improvement of Error Tolerance and Access Efficiency |
| 983 | -- | 996 | Philippe Clauss, Federico Javier Fernández, Diego Garbervetsky, Sven Verdoolaege. Symbolic Polynomial Maximization Over Convex Sets and Its Application to Memory Requirement Estimation |
| 997 | -- | 1007 | Mian Dong, Lin Zhong. Nanowire Crossbar Logic and Standard Cell-Based Integration |
| 1008 | -- | 1020 | Po-Ching Lin, Ying-Dar Lin, Yuan-Cheng Lai, Yi-Jun Zheng, Tsern-Huei Lee. Realizing a Sub-Linear Time String-Matching Algorithm With a Hardware Accelerator Using Bloom Filters |
| 1021 | -- | 1033 | Jong Suk Lee, Dong Sam Ha. FleXilicon Architecture and Its VLSI Implementation |
| 1034 | -- | 1047 | Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi. Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus |
| 1048 | -- | 1060 | Jason Helge Anderson, Farid N. Najm. Low-Power Programmable FPGA Routing Circuitry |
| 1061 | -- | 1072 | Changzhong Chen, Dharmendra Saraswat, Ramachandra Achar, Emad Gad, Michel S. Nakhla, Mustapha Chérif-Eddine Yagoub. Passivity Compensation Algorithm for Method-of-Characteristics-Based Multiconductor Transmission Line Interconnect Macromodels |
| 1073 | -- | 1086 | Renato Fernandes Hentschke, Jagannathan Narasimhan, Marcelo O. Johann, Ricardo Reis. Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff |
| 1087 | -- | 1098 | Ren-Jie Lee, Hung-Ming Chen. Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign |
| 1099 | -- | 1112 | Kendall Ananyi, Hamad Alrimeih, Daler N. Rakhmatov. Flexible Hardware Processor for Elliptic Curve Cryptography Over NIST Prime Fields |
| 1113 | -- | 1126 | Hwisung Jung, Andy Hwang, Massoud Pedram. Predictive-Flow-Queue-Based Energy Optimization for Gigabit Ethernet Controllers |
| 1127 | -- | 1137 | Bo Zhai, Sanjay Pant, Leyla Nazhandali, Scott Hanson, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Todd M. Austin, Dennis Sylvester, David Blaauw. Energy-Efficient Subthreshold Processor Design |
| 1138 | -- | 1142 | Hui Shao, Chi-Ying Tsui, Wing-Hung Ki. The Design of a Micro Power Management System for Applications Using Photovoltaic Cells With the Maximum Output Power Control |
| 1142 | -- | 1147 | Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Xin Yang. Design and Implementation of a Field Programmable CRC Circuit Architecture |
| 1147 | -- | 1151 | Mohammad M. Mansour. A Parallel Pruned Bit-Reversal Interleaver |
| 1152 | -- | 1156 | Po-Lin Chen, Jhih-Wei Lin, Tsin-Yuan Chang. IEEE Standard 1500 Compatible Delay Test Framework |
| 1157 | -- | 1161 | Milos Petrovic, Aleksandra Smiljanic, Milos Blagojevic. Design of the Switching Controller for the High-Capacity Non-Blocking Internet Router |
| 1161 | -- | 1166 | Daniele Rossi, José Manuel Cazeaux, Martin Omaña, Cecilia Metra, Abhijit Chatterjee. Accurate Linear Model for SET Critical Charge Estimation |
| 1166 | -- | 1170 | Youngmin Kim, Dusan Petranovic, Dennis Sylvester. Simple and Accurate Models for Capacitance Considering Floating Metal Fill Insertion |