| 453 | -- | 469 | Niraj K. Jha. Editorial Appointments for the 2009-2010 Term |
| 470 | -- | 472 | Minsu Choi, Fabrizio Lombardi, Nohpill Park. Introduction to the Special Section on Nanocircuits and Systems |
| 473 | -- | 486 | Helia Naeimi, André DeHon. Fault Secure Encoder and Decoder for NanoMemory Applications |
| 487 | -- | 495 | Pinaki Mazumder, Sing-Rong Li, Idongesit E. Ebong. Tunneling-Based Cellular Nonlinear Network Architectures for Image Processing |
| 496 | -- | 506 | William Rhett Davis, Eun Chu Oh, Ambarish M. Sule, Paul D. Franzon. Application Exploration for 3-D Integrated Circuits: TCAM, FIFO, and FFT Case Studies |
| 507 | -- | 516 | Timothy J. Dysart, Peter M. Kogge. Analyzing the Inherent Reliability of Moderately Sized Magnetic and Electrostatic QCA Circuits Via Probabilistic Transfer Matrices |
| 517 | -- | 528 | Kyung Ki Kim, Yong-Bin Kim. A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems |
| 529 | -- | 540 | Jianwei Dai, Lei Wang, Faquir Jain. Analysis of Defect Tolerance in Molecular Crossbar Electronics |
| 541 | -- | 550 | Pramod Kumar Meher. On Efficient Implementation of Accumulation in Finite Field Over GF(2:::m:::) and its Applications |
| 551 | -- | 560 | Chunjie Duan, Victor H. Cordero Calle, Sunil P. Khatri. Efficient On-Chip Crosstalk Avoidance CODEC Design |
| 561 | -- | 570 | Khaled Benkrid, Ying Liu, Abdsamad Benkrid. A Highly Parameterized and Efficient FPGA-Based Skeleton for Pairwise Biological Sequence Alignment |
| 571 | -- | 577 | Hai Qi Liu, Wang Ling Goh, Liter Siek, Wei Meng Lim, Yue-Ping Zhang. A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator With Coarse and Fine Frequency Tuning |
| 578 | -- | 582 | Hassan Hassan, Mohab Anis, Mohamed I. Elmasry. Total Power Modeling in FPGAs Under Spatial Correlation |
| 582 | -- | 587 | Zhiqiang Cui, Zhongfeng Wang, Youjian Liu. High-Throughput Layered LDPC Decoding Architecture |
| 587 | -- | 592 | Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar. Wafer-Level Defect Screening for Big-D/Small-A Mixed-Signal SoCs |