| 161 | -- | 171 | Francesco Menichelli, Mauro Olivieri. Static Minimization of Total Energy Consumption in Memory Subsystem for Scratchpad-Based Systems-on-Chips |
| 172 | -- | 180 | A. D. Grasso, Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti. Analysis and Implementation of a Minimum-Supply Body-Biased CMOS Differential Amplifier Cell |
| 181 | -- | 193 | Jonathan Rosenfeld, Eby G. Friedman. Quasi-Resonant Interconnects: A Low Power, Low Latency Design Methodology |
| 194 | -- | 206 | Koustav Bhattacharya, Nagarajan Ranganathan, Soontae Kim. A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy |
| 207 | -- | 220 | Juan A. Carrasco, Víctor Suñé. An ROBDD-Based Combinatorial Method for the Evaluation of Yield of Defect-Tolerant Systems-on-Chip |
| 221 | -- | 233 | Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis. The ARISE Approach for Extending Embedded Processors With Arbitrary Hardware Accelerators |
| 234 | -- | 247 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt. Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations |
| 248 | -- | 261 | S. F. Nielsen, Jens Sparsø, Jan Madsen. Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend |
| 262 | -- | 268 | Jin Sha, Zhongfeng Wang, Ming-Lun Gao, Li Li. Multi-Gb/s LDPC Code Design and Implementation |
| 269 | -- | 277 | Suganth Paul, Nikhil Jayakumar, Sunil P. Khatri. A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations |
| 278 | -- | 0 | Massimo Alioto, Gaetano Palumbo, Massimo Poli. Analysis and Modeling of Energy Consumption in RLC Tree Circuits |
| 292 | -- | 301 | Jie Gu, Ramesh Harjani, Chris H. Kim. Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs |
| 302 | -- | 306 | M. Mottaghi-Dastjerdi, Ali Afzali-Kusha, Massoud Pedram. BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture |
| 306 | -- | 311 | Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen. A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus |
| 311 | -- | 316 | Jose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi. CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-Chip Interconnects |