| 593 | -- | 603 | Yoonjin Kim, Rabi N. Mahapatra, Ilhyun Park, Kiyoung Choi. Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture |
| 604 | -- | 612 | Nitin Mohan, Manoj Sachdev. Low-Leakage Storage Cells for Ternary Content Addressable Memories |
| 613 | -- | 626 | Pei-Yu Huang, Yu-Min Lee. Full-Chip Thermal Analysis for the Early Design Stage via Generalized Integral Transforms |
| 627 | -- | 637 | Nathaniel J. Guilar, Travis Kleeburg, Albert Chen, Diego R. Yankelevich, Rajeevan Amirtharajah. Integrated Solar Energy Harvesting and Storage |
| 638 | -- | 645 | Sherif A. Tawfik, Volkan Kursun. Low Power and High Speed Multi Threshold Voltage Interface Circuits |
| 646 | -- | 659 | Changyun Zhu, Zhengyu Gu, Robert P. Dick, Li Shang, Robert G. Knobel. Characterization of Single-Electron Tunneling Transistors for Designing Low-Power Embedded Systems |
| 660 | -- | 673 | Felipe Klein, Roberto Leao, Guido Araujo, Luiz C. V. dos Santos, Rodolfo Azevedo. A Multi-Model Engine for High-Level Power Estimation Accuracy Optimization |
| 674 | -- | 687 | Glenn Leary, Krishnan Srinivasan, Krishna Mehta, Karam S. Chatha. Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique |
| 688 | -- | 696 | Min-Sheng Kao, Jen-Ming Wu, Chih-Hsing Lin, Fanta Chen, Ching-Te Chiu, Shawn S. H. Hsu. A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18- /mu m CMOS Technology |
| 697 | -- | 708 | Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty. Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits |
| 709 | -- | 722 | Abdsamad Benkrid, Khaled Benkrid. Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension |
| 723 | -- | 727 | Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou. Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM |
| 728 | -- | 732 | Mirko Loghi, Paolo Azzoni, Massimo Poncino. Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching |