| 957 | -- | 970 | Yuhao Wang, Hao Yu, Wei Zhang. Nonvolatile CBRAM-Crossbar-Based 3-D-Integrated Hybrid Memory for Data Retention |
| 971 | -- | 982 | Mahmood Khayatzadeh, Yong Lian. Average-8T Differential-Sensing Subthreshold SRAM With Bit Interleaving and 1k Bits Per Bitline |
| 983 | -- | 994 | Yansheng Wang, Leibo Liu, Shouyi Yin, Min Zhu, Peng Cao, Jun Yang, Shaojun Wei. On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time |
| 995 | -- | 1003 | Mehran Mozaffari Kermani, Reza Azarderakhsh, Chiou-Yng Lee, Siavash Bayat Sarmadi. m) |
| 1004 | -- | 1015 | Jonghong Kim, Wonyong Sung. Rate-0.96 LDPC Decoding VLSI for Soft-Decision Error Correction of NAND Flash Memory |
| 1016 | -- | 1029 | Xuehui Zhang, Mohammad Tehranipoor. Design of On-Chip Lightweight Sensors for Effective Detection of Recycled ICs |
| 1030 | -- | 1041 | Shuo Wang, Mohammad Tehranipoor. Light-Weight On-Chip Structure for Measuring Timing Uncertainty Induced by Noise in Integrated Circuits |
| 1042 | -- | 1053 | Itamar Levi, Alexander Belenky, Alexander Fish. Logical Effort for CMOS-Based Dual Mode Logic Gates |
| 1054 | -- | 1059 | Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang, Shaojun Wei. Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method |
| 1060 | -- | 1068 | Min-Woo Lee, Ji-Hwan Yoon, Jongsun Park. Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data Priority |
| 1069 | -- | 1081 | Wen-Hsiang Chang, Mango Chia-Tso Chao, Shi-Hao Chen. Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer |
| 1082 | -- | 1095 | Xiaowen Wu, Yaoyao Ye, Jiang Xu, Wei Zhang, Weichen Liu, Mahdi Nikdast, Xuan Wang. UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors |
| 1096 | -- | 1105 | Ching-Che Chung, Duo Sheng, Sung-En Shen. High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology |
| 1106 | -- | 1117 | Saket Gupta, Sachin S. Sapatnekar. Variation-Aware Variable Latency Design |
| 1118 | -- | 1126 | Takashi Kawamoto, Masato Suzuki, Takayuki Noto. 1.9-ps Jitter, 10.0-dBm-EMI Reduction Spread-Spectrum Clock Generator With Autocalibration VCO Technique for Serial-ATA Application |
| 1127 | -- | 1137 | Behzad Dehlaghi, Sebastian Magierowski, Leonid Belostotski. A 12.5-Gb/s On-Chip Oscilloscope to Measure Eye Diagrams and Jitter Histograms of High-Speed Signals |
| 1138 | -- | 1149 | Tseng-Chin Luo, Mango Chia-Tso Chao, Huan-Chi Tseng, Masaharu Goto, Philip A. Fisher, Yuan-Yao Chang, Chi-Min Chang, Takayuki Takao, Katsuhito Iwasaki, Cheng Mao Lee. Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization |
| 1150 | -- | 1163 | Chun-Yi Lee, Niraj K. Jha. FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks |
| 1164 | -- | 1169 | Tien-Yu Lo, Chi-Hsiang Lo. 1-V 365-µW 2.5-MHz Channel Selection Filter for 3G Wireless Receiver in 55-nm CMOS |
| 1170 | -- | 1174 | Minoo Mirsaeedi, Andres J. Torres, Mohab H. Anis. Litho-Friendly Decomposition Method for Self-Aligned Triple Patterning |
| 1174 | -- | 1179 | Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo. Area-Delay Efficient Binary Adders in QCA |
| 1179 | -- | 1182 | Kejie Huang, Ning Ning, Yong Lian. Optimization Scheme to Minimize Reference Resistance Distribution of Spin-Transfer-Torque MRAM |
| 1183 | -- | 1187 | Youngjoo Lee, Hoyoung Yoo, Injae Yoo, In-Cheol Park. High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives |
| 1187 | -- | 1191 | Daejin Park, Tag Gon Kim. Built-In Binary Code Inversion Technique for On-Chip Flash Memory Sense Amplifier With Reduced Read Current Consumption |
| 1192 | -- | 1196 | Jason M. Allred, Sanghamitra Roy, Koushik Chakraborty. Dark Silicon Aware Multicore Systems: Employing Design Automation With Architectural Insight |
| 1197 | -- | 1201 | Junwhan Ahn, Kiyoung Choi. LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology |
| 1202 | -- | 1206 | Sumit Jagdish Darak, Smitha Kavallur Pisharath Gopi, Achutavarrier Prasad Vinod, Edmund Ming-Kit Lai. Low-Complexity Reconfigurable Fast Filter Bank for Multi-Standard Wireless Receivers |