| 2449 | -- | 2461 | Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia. A Variation-Aware Preferential Design Approach for Memory-Based Reconfigurable Computing |
| 2462 | -- | 2475 | Yang Yang, Niraj K. Jha. FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations |
| 2476 | -- | 2487 | Xing Hu, Guihai Yan, Yu Hu, Xiaowei Li 0001. Orchestrator: Guarding Against Voltage Emergencies in Multithreaded Applications |
| 2488 | -- | 2498 | David Esseni, Manuel Guglielmini, Bernard Kapidani, Tommaso Rollo, Massimo Alioto. Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level |
| 2499 | -- | 2512 | Massimo Alioto, David Esseni. Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II-Evaluation at Circuit Level and Design Perspectives |
| 2513 | -- | 2526 | Hamed Tabkhi, Gunar Schirner. Application-Guided Power Gating Reducing Register File Static Power |
| 2527 | -- | 2534 | Inna Vaisband, Mahmood J. Azhar, Eby G. Friedman, Selçuk Köse. Digitally Controlled Pulse Width Modulator for On-Chip Power Management |
| 2535 | -- | 2548 | Bishnu Prasad Das, Hidetoshi Onodera. Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs |
| 2549 | -- | 2560 | Zia Abbas, Antonio Mastrandrea, Mauro Olivieri. A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs |
| 2561 | -- | 2570 | François Botman, David Bol, Jean-Didier Legat, Kaushik Roy. Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits |
| 2571 | -- | 2584 | Kedar Karmarkar, Spyros Tragoudas. Error Correction Encoding for Tightly Coupled On-Chip Buses |
| 2585 | -- | 2595 | Gursharan Reehal, Mohammed Ismail. A Systematic Design Methodology for Low-Power NoCs |
| 2596 | -- | 2606 | Amir Reza Baghban Behrouzian, Nasser Masoumi. Analytical Solutions for Distributed Interconnect Models - Part I: Step Input Response of Finite and Semi-Infinite Lines |
| 2607 | -- | 2620 | Ting-Jung Lin, Wei Zhang, Niraj K. Jha. A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps |
| 2621 | -- | 2628 | Daniel Neil, Shih-Chii Liu. Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator |
| 2629 | -- | 2634 | Jianfeng Zhu, Liyang Pan, Yaru Yan, Dong Wu, Hu He. A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA |
| 2635 | -- | 2648 | Leibo Liu, Dong Wang, Shouyi Yin, Yingjie Chen, Min Zhu, Shaojun Wei. SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration |
| 2649 | -- | 2660 | Jun Lin, Zhiyuan Yan. An Efficient Fully Parallel Decoder Architecture for Nonbinary LDPC Codes |
| 2661 | -- | 2674 | Hamad Alrimeih, Daler N. Rakhmatov. Fast and Flexible Hardware Support for ECC Over Multiple Standard Prime Fields |
| 2675 | -- | 2688 | Chun-Fu Liao, Jhong-Yu Wang, Yuan-Hao Huang. A 3.1 Gb/s 8 × 8 Sorting Reduced K-Best Detector With Lattice Reduction and QR Decomposition |
| 2689 | -- | 2700 | Li-Wei Chai, Po-Lin Chiu, Yuan-Hao Huang. A 2-D Interpolation-Based QRD Processor With Partial Layer Mapping for MIMO-OFDM Systems |
| 2701 | -- | 2712 | Ojas A. Bapat, Paul D. Franzon, Richard M. Fastow. A Generic and Scalable Architecture for a Large Acoustic Model and Large Vocabulary Speech Recognition Accelerator Using Logic on Memory |
| 2713 | -- | 2723 | Douglas Paul, Ramachandra Achar, Michel S. Nakhla, Natalie Nakhla. Addressing Partitioning Issues in Parallel Circuit Simulation |
| 2724 | -- | 2737 | Scott Koziol, Stephen Brink, Jennifer Hasler. A Neuromorphic Approach to Path Planning Using a Reconfigurable Neuron Array IC |
| 2738 | -- | 2751 | Jianxin Fang, Sachin S. Sapatnekar. Incorporating Hot-Carrier Injection Effects Into Timing Analysis for Large Circuits |
| 2752 | -- | 2765 | Yanzhi Wang, Xue Lin, Younghyun Kim, Qing Xie, Massoud Pedram, Naehyuck Chang. Single-Source, Single-Destination Charge Migration in Hybrid Electrical Energy Storage Systems |
| 2766 | -- | 2778 | Wei-Hen Lo, Ang-Chih Hsieh, Chien-Ming Lan, Min-Hsien Lin, TingTing Hwang. Utilizing Circuit Structure for Scan Chain Diagnosis |
| 2779 | -- | 2792 | Liang Shi, Jianhua Li, Qing'an Li, Chun Jason Xue, Chengmo Yang, Xuehai Zhou. A Unified Write Buffer Cache Management Scheme for Flash Memory |