| 2041 | -- | 2053 | Sean Keller, David Money Harris, Alain J. Martin. A Compact Transregional Model for Digital CMOS Circuits Operating Near Threshold |
| 2054 | -- | 2066 | Shahar Kvatinsky, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser. Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies |
| 2067 | -- | 2080 | Henry Wong, Vaughn Betz, Jonathan Rose. Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design |
| 2081 | -- | 2092 | Yury Audzevich, Philip M. Watts, Andrew West, Alan Mujumdar, Simon W. Moore, Andrew W. Moore. Power Optimized Transceivers for Future Switched Networks |
| 2093 | -- | 2102 | Kyongsu Lee, Jae-Yoon Sim. Half-Rate Clock-Embedded Source Synchronous Transceivers in 130-nm CMOS |
| 2103 | -- | 2116 | Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou. PowerRush: An Efficient Simulator for Static Power Grid Analysis |
| 2117 | -- | 2130 | Tuck Boon Chan, Puneet Gupta, Andrew B. Kahng, Liangzhen Lai. Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors |
| 2131 | -- | 2144 | Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel. Globally Constrained Locally Optimized 3-D Power Delivery Networks |
| 2145 | -- | 2155 | Krit Athikulwongse, Mongkol Ekpanyapong, Sung Kyu Lim. Exploiting Die-to-Die Thermal Coupling in 3-D IC Placement |
| 2156 | -- | 2163 | Kyeong-Min Kim, Sewook Hwang, Junyoung Song, Chulwoo Kim. An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator |
| 2164 | -- | 2175 | Behrooz Javid, Payam Heydari. Design and Implementation of a CMOS 4-Bit 12-GS/s Data Acquisition System-On-Chip |
| 2176 | -- | 2180 | Mohammad Gholami, Gholamreza Ardeshir. Jitter of Delay-Locked Loops Due to PFD |
| 2181 | -- | 2191 | Young-sub Yuk, Seungchul Jung, Chul Kim, Hui-Dong Gwon, Sukhwan Choi, Gyu-Hyeong Cho. PSR Enhancement Through Super Gain Boosting and Differential Feed-Forward Noise Cancellation in a 65-nm CMOS LDO Regulator |
| 2192 | -- | 2205 | Yi-Ping Su, Wei-Chung Chen, Yu-Ping Huang, Yu-Huei Lee, Ke-Horng Chen, Hsin-Yu Luo. Pseudo-Ramp Current Balance (PRCB) Technique With Offset Cancellation Control (OCC) in Dual-Phase DC-DC Buck Converter |
| 2206 | -- | 2210 | Alexei Jolondz, Shlomo Weiss, Amit Golander. L1-L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters |
| 2211 | -- | 2215 | Bojan Maric, Jaume Abella, Mateo Valero. Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes |
| 2216 | -- | 2220 | Chung-Yi Li, Chung-Len Lee, Ming-Hong Hu, Hwai-Pwu Chou. A Fast Locking-in and Low Jitter PLLWith a Process-Immune Locking-in Monitor |
| 2220 | -- | 2224 | Howard Tang, Zhuochao Sun, Kin Wai Roy Chew, Liter Siek. A 5.8 nW 9.1-ENOB 1-kS/s Local Asynchronous Successive Approximation Register ADC for Implantable Medical Device |
| 2225 | -- | 2228 | Zhe Feng 0002, Naifeng Jing, Lei He. IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs |
| 2229 | -- | 2233 | Shaoteng Liu, Axel Jantsch, Zhonghai Lu. A Fair and Maximal Allocator for Single-Cycle On-Chip Homogeneous Resource Allocation |
| 2233 | -- | 2237 | C. K. Midhun, Jephy Joy, R. K. Kavitha. High-Speed Dynamic Asynchronous Pipeline: Self-Precharging Style |
| 2238 | -- | 2242 | Juan Núñez, Maria J. Avedillo, José M. Quintana. Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements |