| 1593 | -- | 1600 | Jing Guo, Lei Zhu, Wenyi Liu, Hai Huang, Shanshan Liu, Tianqi Wang, Liyi Xiao, Zhigang Mao. Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology |
| 1601 | -- | 1610 | Xiaole Cui, Xiaoxin Cui, Yewen Ni, Min Miao, Yufeng Jin. An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias |
| 1611 | -- | 1621 | Manqing Mao, Pai-Yu Chen, Shimeng Yu, Chaitali Chakrabarti. A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System |
| 1622 | -- | 1631 | Soon-Chan Kwon, Jong-Min Baek, Jong Moon Choi, Kee-Won Kwon. A Fast and Reliable Cross-Point Three-State/Cell ReRAM |
| 1632 | -- | 1643 | Parham Hosseinzadeh Namin, Roberto Muscedere, Majid Ahmadi. Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields |
| 1644 | -- | 1657 | M. Hassan Najafi, Shiva Jamali-Zavareh, David J. Lilja, Marc D. Riedel, Kia Bazargan, Ramesh Harjani. Time-Encoded Values for Highly Efficient Stochastic Circuits |
| 1658 | -- | 1668 | Serdar Süer Erdem, Tugrul Yanik, Anil Çelebi. A General Digit-Serial Architecture for Montgomery Modular Multiplication |
| 1669 | -- | 1680 | Trong Huynh Bao, Julien Ryckaert, Zsolt Tokei, Abdelkarim Mercha, Diederik Verkest, Aaron Voon-Yew Thean, Piet Wambacq. Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond |
| 1681 | -- | 1693 | Tao-Tao Zhu, Jian-yi Meng, Xiao-Yan Xiang, Xiao-lang Yan. Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT Processor |
| 1694 | -- | 1702 | Jeremy Schlachter, Vincent Camus, Krishna V. Palem, Christian Enz. Design and Applications of Approximate Circuits by Gate-Level Pruning |
| 1703 | -- | 1713 | Yu-Min Lee, Kuan-Te Pan, Chun Chen. NaPer: A TSV Noise-Aware Placer |
| 1714 | -- | 1724 | Cang Liu, Chuan Tang, Zuocheng Xing, Luechao Yuan, Yang Zhang. Hardware Architecture Based on Parallel Tiled QRD Algorithm for Future MIMO Systems |
| 1725 | -- | 1730 | Cheng-Ta Chiang. Design of a CMOS Chlorophyll Concentration Detector Based on Organic Chlorophyll Battery for Measuring Vegetable Chlorophyll Concentration |
| 1731 | -- | 1741 | Sangyun Kim, Hamed Abbasizadeh, Imran Ali, Hongjin Kim, SungHun Cho, YoungGun Pu, Sang-Sun Yoo, MinJae Lee, Keum-Cheol Hwang, Youngoo Yang, Kang-Yoon Lee. An Inductive 2-D Position Detection IC With 99.8% Accuracy for Automotive EMR Gear Control System |
| 1742 | -- | 1755 | Je-Kwang Cho, Sunsik Woo. A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC |
| 1756 | -- | 1766 | Mohammad Taherzadeh-Sani, Said M. Hussain Hussaini, Hamidreza Rezaee-Dehsorkh, Frederic Nabki, Mohamad Sawan. A 170-dB Ω CMOS TIA With 52-pA Input-Referred Noise and 1-MHz Bandwidth for Very Low Current Sensing |
| 1767 | -- | 1773 | Yiping Zhang, Ziou Wang, Canyan Zhu, Lijun Zhang. 28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression |
| 1774 | -- | 1781 | Ravi Shankar R. Velampati, El-Sayed Hasaneen, E. K. Heller, Faquir C. Jain. Floating Gate Nonvolatile Memory Using Individually Cladded Monodispersed Quantum Dots |
| 1782 | -- | 1786 | Suganthi Venkatachalam, Seok-Bum Ko. Design of Power and Area Efficient Approximate Multipliers |
| 1787 | -- | 1791 | Huyen Thi Pham, Hanho Lee. Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes |
| 1792 | -- | 0 | HoonSeok Kim, Chanyoun Won, Paul D. Franzon. Corrections to "Crosstalk-Canceling Multimode Interconnect Using Transmitter Encoding" |