| 501 | -- | 510 | Cheng-En Hsieh, Shen-Iuan Liu. A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient |
| 511 | -- | 523 | Shaohan Liu, Dake Liu. A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G |
| 524 | -- | 534 | Liming Xiu, Xiangye Wei, Yuhai Ma. A Full Digital Fractional- $N$ TAF-FLL for Digital Applications: Demonstration of the Principle of a Frequency-Locked Loop Built on Time-Average-Frequency |
| 535 | -- | 548 | Gaurav Saini, Maryam Shojaei Baghini. A Generic Power Management Circuit for Energy Harvesters With Shared Components Between the MPPT and Regulator |
| 549 | -- | 559 | Donkyu Baek, Naehyuck Chang. Runtime Power Management of Battery Electric Vehicles for Extended Range With Consideration of Driving Time |
| 560 | -- | 572 | Shubham Rai, Jens Trommer, Michael Raitza, Thomas Mikolajick, Walter M. Weber, Akash Kumar 0001. Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors |
| 573 | -- | 586 | Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske. Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization |
| 587 | -- | 600 | Amard Afzalian, Hossein Miar Naimi, Massoud Dousti. What Is the Maximum Achievable Oscillation Frequency in a Specified CMOS Process? |
| 601 | -- | 610 | Marco Simicic, Pieter Weckx, Bertrand Parvais, Philippe Roussel, Ben Kaczer, Georges G. E. Gielen. Understanding the Impact of Time-Dependent Random Variability on Analog ICs: From Single Transistor Measurements to Circuit Simulations |
| 611 | -- | 623 | Xiang Ge, Fan Yang 0001, Hengliang Zhu, Xuan Zeng 0001, Dian Zhou. An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition |
| 624 | -- | 636 | Haomiao Wang, Prabu Thiagaraj, Oliver Sinnen. Harmonic-Summing Module of SKA on FPGA - Optimizing the Irregular Memory Accesses |
| 637 | -- | 650 | Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon. FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs |
| 651 | -- | 664 | Behnam Khaleghi, Behzad Omidi, Hussam Amrouch, Jörg Henkel, Hossein Asadi. Estimating and Mitigating Aging Effects in Routing Network of FPGAs |
| 665 | -- | 678 | Zhiming Zhang, Laurent Njilla, Charles A. Kamhoua, Qiaoyan Yu. Thwarting Security Threats From Malicious FPGA Tools With Novel FPGA-Oriented Moving Target Defense |
| 679 | -- | 690 | Shinwoong Park, Sanjay Raman. Analysis and Optimization of Multisection Capacitive DACs for Mixed-Signal Processing |
| 691 | -- | 699 | Wael Dghais, Malek Souilem, Muhammad Alam. Mixed-Signal Overclocked I/O Buffers Model Abstraction for Signal Integrity Assessment |
| 700 | -- | 710 | Scott Lerner, Isikcan Yilmaz, Baris Taskin. Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors |
| 711 | -- | 723 | Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak. Design and Optimization of Inductive-Coupling Links for 3-D-ICs |
| 724 | -- | 728 | Daewoong Lee, Dongil Lee, Yong Hun Kim, Lee-Sup Kim. A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control |
| 729 | -- | 733 | Arpan Thakkar, Srinivas Theertham, Peeyoosh Mirajkar, Sankaran Aniruddhan. Techniques for Improved Continuous and Discrete Tuning Range in Millimeter-Wave VCOs |
| 734 | -- | 737 | Mehrnaz Ahmadi, Sahand Salamat, Bijan Alizadeh. A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs |
| 738 | -- | 741 | Ausmita Sarker, Mehran Mozaffari Kermani, Reza Azarderakhsh. Hardware Constructions for Error Detection of Number-Theoretic Transform Utilized in Secure Cryptographic Architectures |
| 742 | -- | 746 | Yuqi Wang, Amira Aouina, Hui Li, Ian O'Connor, Gabriela Nicolescu, Sébastien Le Beux. Thermal-Aware Design Method for Laser Group Control in Nanophotonic Interconnects |