Journal: IEEE Trans. VLSI Syst.

Volume 27, Issue 9

1977 -- 1989C.-J. Richard Shi, Aili Wang. Analysis of Bitwise and Samplewise Switched Passive Charge Sharing SAR ADCs
1990 -- 1997Daiguo Xu, Hequan Jiang, Lei Qiu 0002, Xiaoquan Yu, Jianan Wang, Zhengping Zhang, Can Zhu, Shiliu Xu. A Linearity-Enhanced 10-Bit 160-MS/s SAR ADC With Low-Noise Comparator Technique
1998 -- 2007Guanhua Wang, Kexu Sun, Qing Zhang, Salam Elahmadi, Ping Gui. A 43.6-dB SNDR 1-GS/s 3.2-mW SAR ADC With Background-Calibrated Fine and Coarse Comparators in 28-nm CMOS
2008 -- 2020Congyi Zhu, Renrong Liang, Jun Lin, Zhongfeng Wang, Li Li. Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs
2021 -- 2032Prathamesh Khatavkar, Sankaran Aniruddhan. 432 nW per Channel 130 nV/rtHz ECG Acquisition Front End With Multifrequency Chopping
2033 -- 2045Wonyoung Lee, Mincheol Kang, Seokin Hong, Soontae Kim. Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages
2046 -- 2059Liang Chang, Xin Ma, Zhaohao Wang, Youguang Zhang, Yufei Ding, Weisheng Zhao, Yuan Xie 0001. DASM: Data-Streaming-Based Computing in Nonvolatile Memory Architecture for Embedded System
2060 -- 2073Shuo-Han Chen, Yuan-Hao Chang, Yu-Ming Chang, Wei Kuan Shih. mwJFS: A Multiwrite-Mode Journaling File System for MLC NVRAM Storages
2074 -- 2087Shahzad Muzaffar, Ibrahim M. Elfadel. A Domain-Specific Processor Microarchitecture for Energy-Efficient, Dynamic IoT Communication
2088 -- 2095Yupeng Fu, Lianming Li, Dongming Wang, Xuan Wang, Long He. 28-GHz CMOS VCO With Capacitive Splitting and Transformer Feedback Techniques for 5G Communication
2096 -- 2104Irith Pomeranz. Extended Transparent-Scan
2105 -- 2118Cheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy. An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction
2119 -- 2130Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher, Zhi-Hong Mao. Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis
2131 -- 2141Ned Bingham, Rajit Manohar. Self-Timed Adaptive Digit-Serial Addition
2142 -- 2155Fereshteh Jafarzadehpour, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Leonel Sousa. Efficient Modular Adder Designs Based on Thermometer and One-Hot Coding
2156 -- 2169Yuanyong Luo, Yuxuan Wang, Yajun Ha, Zhongfeng Wang, Siyuan Chen, Hongbing Pan. Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base
2170 -- 2179Chaudhry Indra Kumar, Ishant Bhatia, Arvind Kumar Sharma, Deep Sehgal, H. S. Jatana, Anand Bulusu. A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches
2180 -- 2190Freddy Forero, Hector Villacorta, Michel Renovell, Víctor H. Champac. Modeling and Detectability of Full Open Gate Defects in FinFET Technology
2191 -- 2204Khushboo Rani, Hemangee K. Kapoor. Write Variation Aware Buffer Assignment for Improved Lifetime of Non-Volatile Buffers in On-Chip Interconnects
2205 -- 2212Jiyong Woo, Shimeng Yu. Impact of Selector Devices in Analog RRAM-Based Crossbar Arrays for Inference and Training of Neuromorphic System
2213 -- 2221Yidong Liu, Leibo Liu, Fabrizio Lombardi, Jie Han 0001. An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using Stochastic Computing
2222 -- 0Yuanyong Luo, Yuxuan Wang, Yajun Ha, Zhongfeng Wang, Siyuan Chen, Hongbing Pan. Corrections to "Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base"

Volume 27, Issue 8

1731 -- 1741Andrew J. Douglass, Sunil P. Khatri. Fast, Ring-Based Design of 3-D Stacked DRAM
1742 -- 1750Debasri Saha, Susmita Sur-Kolay. Guided GA-Based Multiobjective Optimization of Placement and Assignment of TSVs in 3-D ICs
1751 -- 1759Jiann-Jong Chen, Yuh-Shyan Hwang, Jun-Yi Lin, Yi-Tsen Ku. A Dead-Beat-Controlled Fast-Transient-Response Buck Converter With Active Pseudo-Current-Sensing Techniques
1760 -- 1767Shuenn-Yuh Lee, Zhan-Xian Liao, Chih-Hung Lee. Energy-Harvesting Circuits With a High-Efficiency Rectifier and a Low Temperature Coefficient Bandgap Voltage Reference
1768 -- 1778Venkata Chaitanya Krishna Chekuri, Monodeep Kar, Arvind Singh, Saibal Mukhopadhyay. Autotuning of Integrated Inductive Voltage Regulator Using On-Chip Delay Sensor to Tolerate Process and Passive Variations
1779 -- 1789Albert Ciprut, Eby G. Friedman. Stability of On-Chip Power Delivery Systems With Multiple Low-Dropout Regulators
1790 -- 1798Archit Joshi, Mukul Sarkar. A Low-Pass Filter Bandwidth Adaptation Technique for Phase Interpolators
1799 -- 1810Chihiro Matsui, Ken Takeuchi. Dynamic Adjustment of Storage Class Memory Capacity in Memory-Resource Disaggregated Hybrid Storage With SCM and NAND Flash Memory
1811 -- 1818Kwangmin Kim, Seokjoon Kang, Byungsub Kim. A Code Inversion Encoding Technique to Improve Read Margin of A Cross-Point Phase Change Memory
1819 -- 1827Randy W. Mann, Meixiong Zhao, Sanjay Parihar, Qun Gao, Ankur Arya, Carl Radens, Shesh Mani Pandey, Joseph Versaggi, Jack M. Higman, Rick Carter. An Extrinsic Device and Leakage Mechanism in Advanced Bulk FinFET SRAM
1828 -- 1839Junyoung Ko, Younghwi Yang, Jisu Kim, Cheon An Lee, Young-Sun Min, Jin-Young Chun, Moosung Kim, Seong-Ook Jung. Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory
1840 -- 1850Jisu Min, Cheol Kim, Sung Yong Kim, Kee-Won Kwon. A Study of Read Margin Enhancement for 3T2R Nonvolatile TCAM Using Adaptive Bias Training
1851 -- 1860Bi-Wu, Beibei Zhang, Yuanqing Cheng, Ying Wang 0001, Dijun Liu, Weisheng Zhao. An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design
1861 -- 1873Duy Thanh Nguyen, Tuan Nghia Nguyen, Hyun Kim, Hyuk-Jae Lee. A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection
1874 -- 1885Xiaocong Lian, Zhenyu Liu 0001, Zhourui Song, Jiwu Dai, Wei Zhou 0020, Xiangyang Ji. High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic
1886 -- 1896Seongjong Kim, Joao Pedro Cerqueira, Mingoo Seok. A Near-Threshold Spiking Neural Network Accelerator With a Body-Swapping-Based In Situ Error Detection and Correction Technique
1897 -- 1906Aayush Ankit, Minsuk Koo, Shreyas Sen, Kaushik Roy 0001. Powerline Communication for Enhanced Connectivity in Neuromorphic Systems
1907 -- 1920Eberle A. Rambo, Yunsheng Shang, Rolf Ernst. Providing Integrity in Real-Time Networks-on-Chip
1921 -- 1932Tao-Chun Yu, An-Jie Shih, Shao-Yun Fang. Flip-Chip Routing With I/O Planning Considering Practical Pad Assignment Constraints
1933 -- 1946Kyeongrok Jo, Seyong Ahn, Jungho Do, Taejoong Song, Taewhan Kim, Kyu-Myung Choi. Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization
1947 -- 1951Libo Qian, Kefang Qian, Xitao He, Zhufei Chu, Yidie Ye, Shi Ge, Yinshui Xia. Through-Silicon Via-Based Capacitor and Its Application in LDO Regulator Design
1952 -- 1956Pedro Reviriego, Anees Ullah, Salvatore Pontarelli. PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration
1957 -- 1961Myeongjin Kim, Wontaeck Jung, Hyukjun Lee, Eui-Young Chung. A Novel NAND Flash Memory Architecture for Maximally Exploiting Plane-Level Parallelism
1962 -- 1966Olivier Muller, Adrien Prost-Boucle, Alban Bourge, Frédéric Pétrot. Efficient Decompression of Binary Encoded Balanced Ternary Sequences
1967 -- 1971Rafael Sanchotene Silva, Lucas Pereira Luiz, Márcio Cherem Schneider, Carlos Galup-Montoro. A Test Chip for Characterization of the Series Association of MOSFETs
1972 -- 1976Jihye Kim, Sangjun Lee, Sungho Kang. Test-Friendly Data-Selectable Self-Gating (DSSG)

Volume 27, Issue 7

1485 -- 0Massimo Alioto. Editorial: TVLSI Keynote Papers Enriching Our Transactions With Invited Contributions
1486 -- 1503Giovanni V. Resta, Alessandra Leonhardt, Yashwanth Balaji, Stefan De Gendt, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. Devices and Circuits Using Novel 2-D Materials: A Perspective for Future VLSI Systems
1504 -- 1512Hasan Ulusan, Salar Chamanian, Bedirhan Ilik, Ali Muhtaroglu, Haluk Külah. Fully Implantable Cochlear Implant Interface Electronics With 51.2- $\mu$ W Front-End Circuit
1513 -- 1526Yuan Liang, Chirn Chye Boon, Chenyang Li, Xiao-Lan Tang, Herman Jalli Ng, Dietmar Kissinger, Yong Wang, Qingfeng Zhang, Hao Yu. Design and Analysis of $D$ -Band On-Chip Modulator and Signal Source Based on Split-Ring Resonator
1527 -- 1536Jeng-Han Tsai. Design of a 5.3-GHz 31.3-dBm Fully Integrated CMOS Power Amplifier Using Folded Splitting and Combining Architecture
1537 -- 1547Anil Kumar Gundu, Volkan Kursun. Low Leakage Clock Tree With Dual-Threshold- Voltage Split Input-Output Repeaters
1548 -- 1560Christopher Williams 0003, Diaaeldin Abdelrahman, Xiangdong Jia, Abdullah Ibn Abbas, Odile Liboiron-Ladouceur, Glenn E. R. Cowan. Reconfiguration in Source-Synchronous Receivers for Short-Reach Parallel Optical Links
1561 -- 1574Luong N. Nguyen, Chia-Lin Cheng, Milos Prvulovic, Alenka G. Zajic. Creating a Backscattering Side Channel to Enable Detection of Dormant Hardware Trojans
1575 -- 1586Uthman Alsaiari, Fayez Gebali. Hardware Trojan Detection Using Reconfigurable Assertion Checkers
1587 -- 1600Debapriya Basu Roy, Debdeep Mukhopadhyay. High-Speed Implementation of ECC Scalar Multiplication in GF(p) for Generic Montgomery Curves
1601 -- 1613Amin Norollah, Danesh Derafshi, Hakem Beitollahi, Mahdi Fazeli. RTHS: A Low-Cost High-Performance Real-Time Hardware Sorter, Using a Multidimensional Sorting Algorithm
1614 -- 1622Jeng-Shyang Pan, Chiou-Yng Lee, Anissa Sghaier, Zeghid Medien, Jiafeng Xie. Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach
1623 -- 1632Shirshendu Roy, Debiprasad Priyabrata Acharya, Ajit Kumar Sahoo. Low-Complexity Architecture of Orthogonal Matching Pursuit Based on QR Decomposition
1633 -- 1639Somayeh Rahimipour, Runjie Zhang, Ke Wang 0011, Kevin Skadron, Fakhrul Zaman Rokhani, Mircea R. Stan. MTTF Enhancement Power-C4 Bump Placement Optimization
1640 -- 1651Dae-Hyun Kim, Shu-Han Hsu, Linda Milor. Optimization of Experimental Designs for System- Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown
1652 -- 1665Sami Salamin, Victor M. van Santen, Hussam Amrouch, Narendra Parihar, Souvik Mahapatra, Jörg Henkel. Modeling the Interdependences Between Voltage Fluctuation and BTI Aging
1666 -- 1674Zeyu Sun, Sheriff Sadiqbatcha, Hengyang Zhao, Sheldon X.-D. Tan. Saturation-Volume Estimation for Multisegment Copper Interconnect Wires
1675 -- 1684Nezam Rohbani, Hiroaki Gau, Sara Mohammadinejad, Tapas Kumar Maiti, Dondee Navarro, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Hirotaka Takatsuka. Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width Values
1685 -- 1696Govind Radhakrishnan, Youngki Yoon, Manoj Sachdev. A Parametric DFT Scheme for STT-MRAMs
1697 -- 1710Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori. A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM
1711 -- 1719Fabrizio Riente, Daniel Melis, Marco Vacca. Exploring the 3-D Integrability of Perpendicular Nanomagnet Logic Technology
1720 -- 1724Irith Pomeranz. Test Scores for Improving the Accuracy of Logic Diagnosis for Multiple Defects
1725 -- 1729Yi-An Chang, Shen-Iuan Liu. A 13.4-MHz Relaxation Oscillator With Temperature Compensation

Volume 27, Issue 6

1239 -- 1252Huanyu Wang, Qihang Shi, Domenic Forte, Mark M. Tehranipoor. Probing Assessment Framework and Evaluation of Antiprobing Solutions
1253 -- 1261Ahish Shylendra, Swarup Bhunia, Amit Ranjan Trivedi. An Intrinsic and Database-Free Authentication by Exploiting Process Variation in Back-End Capacitors
1262 -- 1275Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz. Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design Flows
1276 -- 1283Tianwen Li, Hongjin Liu, Haigang Yang. Design and Characterization of SEU Hardened Circuits for SRAM-Based FPGA
1284 -- 1297Jakub Siast, Adam Luczak, Marek Domanski. RingNet: A Memory-Oriented Network-On-Chip Designed for FPGA
1298 -- 1307Inayat Ullah, Zahid Ullah, Umar Afzaal, Jeong-A Lee. DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates
1308 -- 1321Daniel Kraak, Mottaqiallah Taouil, Innocent Agbo, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor. Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM
1322 -- 1328Jeetendra Singh, Balwinder Raj. Design and Investigation of 7T2M-NVSRAM With Enhanced Stability and Temperature Impact on Store/Restore Energy
1329 -- 1342Nour Sayed, Rajendra Bishnoi, Mehdi Baradaran Tahoori. Fast and Reliable STT-MRAM Using Nonuniform and Adaptive Error Detecting and Correcting Scheme
1343 -- 1352Gyuseong Kang, Jongsun Park 0001. Charge-Recycling-Based Redundant Write Prevention Technique for Low-Power SOT-MRAM
1353 -- 1364Anindita Paul, Jaime Ramírez-Angulo, Antonio Torralba 0002. Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate
1365 -- 1377Baibhab Chatterjee, Priyadarshini Panda, Shovan Maity, Ayan Biswas, Kaushik Roy 0001, Shreyas Sen. Exploiting Inherent Error Resiliency of Deep Neural Networks to Achieve Extreme Energy Efficiency Through Mixed-Signal Neurons
1378 -- 1389Xu Meng, Lianhong Zhou, Fujiang Lin, Chun-Huat Heng. A Low-Noise Digital-to-Frequency Converter Based on Injection-Locked Ring Oscillator and Rotated Phase Selection for Fractional- $N$ Frequency Synthesis
1390 -- 1403Song-Nien Tang, Fu-Chiang Jan. Energy-Efficient and Calibration-Aware Fourier-Domain OCT Imaging Processor
1404 -- 1415Eduardo Weber Wächter, Cedric de Bellefroid, Basireddy Karunakar Reddy, Amit Kumar Singh, Bashir M. Al-Hashimi, Geoff V. Merrett. Predictive Thermal Management for Energy-Efficient Execution of Concurrent Applications on Heterogeneous Multicores
1416 -- 1427Yao Xiao, Shahin Nazarian, Paul Bogdan. Self-Optimizing and Self-Programming Computing Systems: A Combined Compiler, Complex Networks, and Machine Learning Approach
1428 -- 1437Irith Pomeranz. Extracting a Close-to-Minimum Multicycle Functional Broadside Test Set From a Functional Test Sequence
1438 -- 1449P. R. Chithira, Vinita Vasudevan. Potential Critical Path Selection Based on a Time-Varying Statistical Timing Analysis Framework
1450 -- 1454Ding-Yuan Lee, Ching-Che Wang, An-Yeu Wu. Bundle-Updatable SRAM-Based TCAM Design for OpenFlow-Compliant Packet Processor
1455 -- 1459Suhong Moon, Kwanghyun Shin, Dongsuk Jeon. Enhancing Reliability of Analog Neural Network Processors
1460 -- 1464Georgios Zervakis, Konstantina Koliogeorgi, Dimitrios Anagnostos, Nikolaos Zompakis, Kostas Siozios. VADER: Voltage-Driven Netlist Pruning for Cross-Layer Approximate Arithmetic Circuits
1465 -- 1469Muhammad Avais Qureshi, Hyeonggyu Kim, Soontae Kim. A Restore-Free Mode for MLC STT-RAM Caches
1470 -- 1474Liang Wen, Yuejun Zhang, Xiaoyang Zeng. Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction
1475 -- 1479Shao-I Chu, Chen-En Hsieh, Yu-Jung Huang. Design of FSM-Based Function With Reduced Number of States in Integral Stochastic Computing
1480 -- 1484Tejinder Singh Sandhu, Kamal El-Sankary. Supply-Insensitive Digitally Controlled Delay Lines for 3-D IC Clock Synchronization Architectures

Volume 27, Issue 5

993 -- 1006Manas Kumar Lenka, Gaurab Banerjee. A Wideband Blocker-Tolerant Receiver With Frequency-Translational Resistive Feedback
1007 -- 1016Omar Elsayed, Jorge Zarate-Roldan, Amr Abuellil, Faisal Abdel-Latif Hussien, Ahmed Eladawy, Edgar Sánchez-Sinencio. Highly Linear Low-Power Wireless RF Receiver for WSN
1017 -- 1028Tutu Wan, Yasha Karimi, Milutin Stanacevic, Emre Salman. AC Computing Methodology for RF-Powered IoT Devices
1029 -- 1042Heikki Kultala, Timo Viitanen, Heikki Berg, Pekka Jääskeläinen, Joonas Multanen, Mikko Kokkonen, Kalle Raiskila, Tommi Zetterman, Jarmo Takala. LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor
1043 -- 1052Yuejun Zhang, Zhao Pan 0001, Pengjun Wang, Dailu Ding, Qiaoyan Yu. A 0.1-pJ/b and ACF <0.04 Multiple-Valued PUF for Chip Identification Using Bit-Line Sharing Strategy in 65-nm CMOS
1053 -- 1066Sandhya Koteshwara, Amitabh Das, Keshab K. Parhi. Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption Algorithms
1067 -- 1079Michael Weiner, Wolfgang Wieser, Emili Lupon, Georg Sigl, Salvador Manich. A Calibratable Detector for Invasive Attacks
1080 -- 1092Partha De, Chittaranjan Mandal 0002, Udaya Prampalli. Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks
1093 -- 1104Yushan Jiang, Dong Wang 0006, Pak Kwong Chan. A Quiescent 407-nA Output-Capacitorless Low-Dropout Regulator With 0-100-mA Load Current Range
1105 -- 1113Yaqub Mahnashi, Fang Z. Peng. A Monolithic Voltage-Scalable Fibonacci Switched-Capacitor DC-DC Converter With Intrinsic Parasitic Charge Recycling
1114 -- 1123Abdulqader Mahmoud, Mohammad Alhawari, Baker Mohammad, Hani H. Saleh, Mohammed Ismail 0001. A Gain-Controlled, Low-Leakage Dickson Charge Pump for Energy-Harvesting Applications
1124 -- 1137Swati Bhardwaj, Shashank Raghuraman, Amit Acharyya. Simplex FastICA: An Accelerated and Low Complex Architecture Design Methodology for $n$ D FastICA
1138 -- 1147Hareesh-Reddy Basireddy, Karthikeya Challa, Tooraj Nikoubin. Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures
1148 -- 1160Mario Garrido, Jesús Grajal, Oscar Gustafsson. Optimum Circuits for Bit-Dimension Permutations
1161 -- 1173Shaghayegh Vahdat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram. TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier
1174 -- 1185Qinghui Hong, Qiujie Wu, Xiaoping Wang, Zhigang Zeng. Novel Nonlinear Function Shift Method for Generating Multiscroll Attractors Using Memristor-Based Control Circuit
1186 -- 1195John Vista, Ashish Ranjan. A Simple Floating MOS-Memristor for High-Frequency Applications
1196 -- 1205Pavan Kumar Javvaji, Spyros Tragoudas. On the Sensitization Probability of a Critical Path Considering Process Variations and Path Correlations
1206 -- 1217Hadi Ahmadi Balef, Hamed Fatemi, Kees Goossens, José Pineda de Gyvez. Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention
1218 -- 1222Bo-Cheng Lai, Jyun-Wei Pan, Chien-Yu Lin. Enhancing Utilization of SIMD-Like Accelerator for Sparse Convolutional Neural Networks
1223 -- 1227Subrahmanyam Mula, Vinay Chakravarthi Gogineni, Anindya Sundar Dhar. Robust Proportionate Adaptive Filter Architectures Under Impulsive Noise
1228 -- 1232Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas. Four-Level Forms for Memristive Material Implication Logic
1233 -- 1237Sami Ur Rehman, Mohammad Mahdi Khafaji, Corrado Carta, Frank Ellinger. A 10-Gb/s 20-ps Delay-Range Digitally Controlled Differential Delay Element in 45-nm SOI CMOS
1238 -- 0Manas Kumar Lenka, Gaurab Banerjee. Corrections Corrections to "A Wideband Blocker-Tolerant Receiver With Frequency-Translational Resistive Feedback"

Volume 27, Issue 4

747 -- 756Thinh Hung Pham, Phong Tran, Siew Kei Lam. High-Throughput and Area-Optimized Architecture for rBRIEF Feature Extraction
757 -- 768Tianchan Guan, Xiaoyang Zeng, Mingoo Seok. Recursive Synaptic Bit Reuse: An Efficient Way to Increase Memory Capacity in Associative Memory
769 -- 777Duncan J. M. Moss, David Boland, Philip H. W. Leong. A Two-Speed, Radix-4, Serial-Parallel Multiplier
778 -- 789Siyuan Xu, Benjamin Carrión Schäfer. Toward Self-Tunable Approximate Computing
790 -- 798Dina M. Ellaithy, Magdy A. El-Moursy, Amal Zaki, Abdelhalim Zekry. Dual-Channel Multiplier for Piecewise-Polynomial Function Evaluation for Low-Power 3-D Graphics
799 -- 809Nitish Kumar Srivastava, Rajit Manohar. Operation-Dependent Frequency Scaling Using Desynchronization
810 -- 820Christopher Cowan. Drafting in Self-Timed Circuits
821 -- 829Takao Oshita, Jonathan Douglas, Arun Krishnamoorthy. High-Volume Testing and DC Offset Trimming Technique of On-Die Bandgap Voltage Reference for SOCs and Microprocessors
830 -- 842Shirin Pourashraf, Jaime Ramírez-Angulo, Jose Maria Hinojo Montero, Ramón González Carvajal, Antonio J. López-Martín. ±0.25-V Class-AB CMOS Capacitance Multiplier and Precision Rectifiers
843 -- 853Bing Li 0011, Ji-Ping Na, Wei Wang 0165, Jia Liu 0011, Qian Yang, Pui-In Mak. A 13-bit 8-kS/s Δ-Σ Readout IC Using ZCB Integrators With an Embedded Resistive Sensor Achieving 1.05-pJ/Conversion Step and a 65-dB PSRR
854 -- 863Xuan Dong 0003, Lihong Zhang. EA-Based LDE-Aware Fast Analog Layout Retargeting With Device Abstraction
864 -- 874Weicheng Liu, Can Sitik, Emre Salman, Baris Taskin, Savithri Sundareswaran, Benjamin Huang. SLECTS: Slew-Driven Clock Tree Synthesis
875 -- 887Sebastian Huhn 0001, Stefan Frehse, Robert Wille, Rolf Drechsler. Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits
888 -- 898Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim. System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs
899 -- 912Abdullah Guler, Niraj K. Jha. Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage
913 -- 926Christian Pilato, Kanad Basu, Francesco Regazzoni, Ramesh Karri. Black-Hat High-Level Synthesis: Myth or Reality?
927 -- 939Hadi Jahanirad. CC-SPRA: Correlation Coefficients Approach for Signal Probability-Based Reliability Analysis
940 -- 953Han Zhou, Zeyu Sun, Sheriff Sadiqbatcha, Naehyuck Chang, Sheldon X.-D. Tan. EM-Aware and Lifetime-Constrained Optimization for Multisegment Power Grid Networks
954 -- 963Yintang Yang, Ke Chen, Huaxi Gu, Bowen Zhang, Lijing Zhu. TAONoC: A Regular Passive Optical Network-on-Chip Architecture Based on Comb Switches
964 -- 968Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto. Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation
969 -- 973Yi-An Chang, Trio Adiono, Amy Hamidah, Shen-Iuan Liu. An On-Chip Relaxation Oscillator With Comparator Delay Compensation
974 -- 977Jusung Kim, Han-Shin Jo, Kyoung-Jae Lee, Dong-Ho Lee, Dae-Hyun Choi, Sangkil Kim. A Low-Complexity I/Q Imbalance Calibration Method for Quadrature Modulator
978 -- 982Joo-Hyung Chae, Hyeongjun Ko, Jihwan Park, Suhwan Kim. A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator
983 -- 987Safwat Mostafa Noor, Eugene John, Manoj Panday. Design and Implementation of an Ultralow-Energy FFT ASIC for Processing ECG in Cardiac Pacemakers
988 -- 991Panni Wang, Feng Xu, Bo Wang, Bin Gao, Huaqiang Wu, He Qian, Shimeng Yu. Three-Dimensional nand Flash for Vector-Matrix Multiplication

Volume 27, Issue 3

501 -- 510Cheng-En Hsieh, Shen-Iuan Liu. A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient
511 -- 523Shaohan Liu, Dake Liu. A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G
524 -- 534Liming Xiu, Xiangye Wei, Yuhai Ma. A Full Digital Fractional- $N$ TAF-FLL for Digital Applications: Demonstration of the Principle of a Frequency-Locked Loop Built on Time-Average-Frequency
535 -- 548Gaurav Saini, Maryam Shojaei Baghini. A Generic Power Management Circuit for Energy Harvesters With Shared Components Between the MPPT and Regulator
549 -- 559Donkyu Baek, Naehyuck Chang. Runtime Power Management of Battery Electric Vehicles for Extended Range With Consideration of Driving Time
560 -- 572Shubham Rai, Jens Trommer, Michael Raitza, Thomas Mikolajick, Walter M. Weber, Akash Kumar 0001. Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors
573 -- 586Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske. Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization
587 -- 600Amard Afzalian, Hossein Miar Naimi, Massoud Dousti. What Is the Maximum Achievable Oscillation Frequency in a Specified CMOS Process?
601 -- 610Marco Simicic, Pieter Weckx, Bertrand Parvais, Philippe Roussel, Ben Kaczer, Georges G. E. Gielen. Understanding the Impact of Time-Dependent Random Variability on Analog ICs: From Single Transistor Measurements to Circuit Simulations
611 -- 623Xiang Ge, Fan Yang 0001, Hengliang Zhu, Xuan Zeng 0001, Dian Zhou. An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition
624 -- 636Haomiao Wang, Prabu Thiagaraj, Oliver Sinnen. Harmonic-Summing Module of SKA on FPGA - Optimizing the Irregular Memory Accesses
637 -- 650Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon. FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs
651 -- 664Behnam Khaleghi, Behzad Omidi, Hussam Amrouch, Jörg Henkel, Hossein Asadi. Estimating and Mitigating Aging Effects in Routing Network of FPGAs
665 -- 678Zhiming Zhang, Laurent Njilla, Charles A. Kamhoua, Qiaoyan Yu. Thwarting Security Threats From Malicious FPGA Tools With Novel FPGA-Oriented Moving Target Defense
679 -- 690Shinwoong Park, Sanjay Raman. Analysis and Optimization of Multisection Capacitive DACs for Mixed-Signal Processing
691 -- 699Wael Dghais, Malek Souilem, Muhammad Alam. Mixed-Signal Overclocked I/O Buffers Model Abstraction for Signal Integrity Assessment
700 -- 710Scott Lerner, Isikcan Yilmaz, Baris Taskin. Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors
711 -- 723Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak. Design and Optimization of Inductive-Coupling Links for 3-D-ICs
724 -- 728Daewoong Lee, Dongil Lee, Yong Hun Kim, Lee-Sup Kim. A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control
729 -- 733Arpan Thakkar, Srinivas Theertham, Peeyoosh Mirajkar, Sankaran Aniruddhan. Techniques for Improved Continuous and Discrete Tuning Range in Millimeter-Wave VCOs
734 -- 737Mehrnaz Ahmadi, Sahand Salamat, Bijan Alizadeh. A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs
738 -- 741Ausmita Sarker, Mehran Mozaffari Kermani, Reza Azarderakhsh. Hardware Constructions for Error Detection of Number-Theoretic Transform Utilized in Secure Cryptographic Architectures
742 -- 746Yuqi Wang, Amira Aouina, Hui Li, Ian O'Connor, Gabriela Nicolescu, Sébastien Le Beux. Thermal-Aware Design Method for Laser Group Control in Nanophotonic Interconnects

Volume 27, Issue 2

253 -- 280Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han 0001, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu 0001, Wei Zhang 0012, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber. Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory
281 -- 293Guillaume Renaud, Mamadou Diallo, Manuel J. Barragan, Salvador Mir. Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs
294 -- 303Anindita Paul, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal. CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency
304 -- 315Nicolas Laflamme-Mayer, Gilbert Kowarzyk, Yves Blaquière, Yvon Savaria, Mohamad Sawan. A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration
316 -- 325Tomasz Kulej, Fabian Khateb, Luis H. C. Ferreira. A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta-Sigma Modulator in 0.18-µm CMOS
326 -- 336Chih-Wen Lu, Ping-Yeh Yin, Mu-Yong Lin. A 10-bit Two-Stage R-DAC With Isolating Source Followers for TFT-LCD and AMOLED Column-Driver ICs
337 -- 349Yang Zhang, Debajit Basak, Kong-Pang Pun. Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI
350 -- 363Kshitij Bhardwaj, Steven M. Nowick. A Continuous-Time Replication Strategy for Efficient Multicast in Asynchronous NoCs
364 -- 375Mohammad A. Usmani, Shahrzad Keshavarz, Eric Matthews, Lesley Shannon, Russell Tessier, Daniel E. Holcomb. Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration
376 -- 386Shivani Bathla, Rahul M. Rao, Nitin Chandrachoodan. A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits
387 -- 397Sara Choi, Hong Keun Ahn, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung. A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories
398 -- 406Pratheep Bondalapati, Won Namgoong. Timing Jitter Distribution and Power Spectral Density of a Second-Order Bang-Bang Digital PLL With Transport Delay Using Fokker-Planck Equations
407 -- 415Chunyu Peng, Jiati Huang, Changyong Liu, Qiang Zhao, Songsong Xiao, Xiulong Wu, Zhiting Lin, Junning Chen, Xuan Zeng 0001. Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application
416 -- 429Md. Badruddoja Majumder, Md Sakib Hasan, Mesbah Uddin, Garrett S. Rose. A Secure Integrity Checking System for Nanoelectronic Resistive RAM
430 -- 443Murali K. Rajendran, V. Priya, Shourya Kansal, Gajendranath Chowdary, Ashudeb Dutta. A 100-mV-2.5-V Burst Mode Constant on-Time- Controlled Battery Charger With 92% Peak Efficiency and Integrated FOCV Technique
444 -- 457Zahi Moudallal, Farid N. Najm. Power Scheduling With Active RC Power Grids
458 -- 467Qin Wang, Zechen Liu, Jian-Fei Jiang, Naifeng Jing, Weiguang Sheng. A New Cellular-Based Redundant TSV Structure for Clustered Faults
468 -- 480Panagiotis Chaourani, Saul Rodriguez, Per-Erik Hellstrom, Ana Rusu. Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines
481 -- 485Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins. Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector
486 -- 490Pedro Reviriego, Salvatore Pontarelli, Anees Ullah. Error Detection and Correction in SRAM Emulated TCAMs
491 -- 495Elena Ioana Vatajelu, Giorgio Di Natale. High-Entropy STT-MTJ-Based TRNG
496 -- 500Irith Pomeranz. Test Compaction by Test Removal Under Transparent Scan

Volume 27, Issue 12

2703 -- 2705Prabhat Mishra, Debdeep Mukhopadhyay, Swarup Bhunia. Guest Editorial: Special Section on Autonomous Intelligence for Security and Privacy Analytics
2706 -- 2719Rana Elnaggar, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori. Hardware Trojan Detection Using Changepoint-Based Anomaly Detection Techniques
2720 -- 2733Anupam Golder, Debayan Das, Josef Danial, Santosh Ghosh, Shreyas Sen, Arijit Raychowdhury. Practical Approaches Toward Deep-Learning-Based Cross-Device Power Side-Channel Attack
2734 -- 2744Vojtech Mrazek, Lukás Sekanina, Roland Dobai, Marek Sýs, Petr Svenda. Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques
2745 -- 2754Jingyan Fu, Zhiheng Liao, Jinhui Wang. Memristor-Based Neuromorphic Hardware Improvement for Privacy-Preserving ANN
2755 -- 2766Mohammed Shayan, Sukanta Bhattacharjee, Yong-Ak Song, Krishnendu Chakrabarty, Ramesh Karri. Toward Secure Microfluidic Fully Programmable Valve Array Biochips
2767 -- 2780Wei Zeng, Boyu Zhang 0001, Azadeh Davoodi. Analysis of Security of Split Manufacturing Using Machine Learning
2781 -- 2791Abhishek Vashist, Andrew Keats, Sai Manoj Pudukotai Dinakarrao, Amlan Ganguly. Securing a Wireless Network-on-Chip Against Jamming-Based Denial-of-Service and Eavesdropping Attacks
2792 -- 2801Zhaojun Lu, Qian Wang, Gang Qu, Haichun Zhang, Zhenglin Liu. A Blockchain-Based Privacy-Preserving Authentication Scheme for VANETs
2802 -- 2815Stjepan Picek, Annelie Heuser, Alan Jovic, Lejla Batina. A Systematic Evaluation of Profiling Through Focused Feature Selection
2816 -- 2828S. Kala, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan. High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture
2829 -- 2841Rajat Sadhukhan, Nilanjan Datta, Debdeep Mukhopadhyay. Power Efficiency of S-Boxes: From a Machine-Learning-Based Tool to a Deterministic Model
2842 -- 2854Sumit K. Mandal, Ganapati Bhat, Chetan Arvind Patil, Janardhan Rao Doppa, Partha Pratim Pande, Ümit Y. Ogras. Dynamic Resource Management of Heterogeneous Mobile Platforms via Imitation Learning
2855 -- 2860Yuhua Liang, Zhangming Zhu, Xueqing Li, Sumeet Kumar Gupta, Suman Datta, Vijaykrishnan Narayanan. Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances
2861 -- 2871Wookpyo Hong, Bai Nguyen, Zhiyuan Zhou, Nghia Tang, Jong-Hoon Kim, Partha Pratim Pande, Deukhyoun Heo. A Dual-Output Step-Down Switched-Capacitor Voltage Regulator With a Flying Capacitor Crossing Technique for Enhanced Power Efficiency
2872 -- 2883Yongkang Tang, Shaoqing Li, Liang Fang, Xiao Hu, Jihua Chen. Golden-Chip-Free Hardware Trojan Detection Through Quiescent Thermal Maps
2884 -- 2896Xiaoxiao Wang, Yueying Han, Mark Tehranipoor. System-Level Counterfeit Detection Using On-Chip Ring Oscillator Array
2897 -- 2910Md Mahbub Alam, Mark Tehranipoor, Domenic Forte. Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization and Voltage Scaling
2911 -- 2924Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan. Formal Modeling and Verification of PCHB Asynchronous Circuits
2925 -- 2938M. Hassan Najafi, Devon Jenson, David J. Lilja, Marc D. Riedel. Performing Stochastic Computation Deterministically
2939 -- 2943Jiaquan Wu, Feiteng Li, Zhijian Chen, Xiaoyan Xiang. A 3.89-GOPS/mW Scalable Recurrent Neural Network Processor With Improved Efficiency on Memory and Computation
2944 -- 2948Soon-Won Kwon, Hyeon-Min Bae. A Fully Digital Semirotational Frequency Detection Algorithm for Bang-Bang CDRs
2949 -- 2953Ruikuan Lu, A. K. M. Arifuzzman, Md Kamal Hossain, Steven D. Gardner, Sazia A. Eliza, J. Iwan D. Alexander, Yehia Massoud, Mohammad Rafiqul Haider. A Low-Power Sensitive Integrated Sensor System for Thermal Flow Monitoring
2954 -- 2958Yun Fang, Zhong Tang, Xiao-peng Yu, Zheng Shi, Kiat Seng Yeo. A Reliability-Oriented Startup Analysis of Injection-Locked Frequency Divider Based on Broken Symmetry Theory

Volume 27, Issue 11

2469 -- 2472Anupam Chattopadhyay, Swaroop Ghosh, Wayne Burleson, Debdeep Mukhopadhyay. Guest Editorial Special Section on Security Challenges and Solutions With Emerging Computing Technologies
2473 -- 2484Ben Perach, Shahar Kvatinsky. An Asynchronous and Low-Power True Random Number Generator Using STT-MTJ
2485 -- 2497Ting-Sheng Chen, Kai-Ni Hou, Win-Ken Beh, An-Yeu Wu. Low-Complexity Compressed-Sensing-Based Watermark Cryptosystem and Circuits Implementation for Wireless Sensor Networks
2498 -- 2510Lukas Zimmermann, Alexander Scholz, Mehdi Baradaran Tahoori, Jasmin Aghassi-Hagmann, Axel Sikora. Design and Evaluation of a Printed Analog-Based Differential Physical Unclonable Function
2511 -- 2522Samir Ben Dodo, Rajendra Bishnoi, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori. A Spintronics Memory PUF for Resilience Against Cloning Counterfeit
2523 -- 2535Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Rolf Drechsler, Ramesh Karri. Reversible Circuits: IC/IP Piracy Attacks and Countermeasures
2536 -- 2547Yanping Gong, Fengyu Qian, Lei Wang 0003. Design for Test and Hardware Security Utilizing Retention Loss of Memristors
2548 -- 2555Taehui Na, Byungkyu Song, Sara Choi, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung. Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS
2556 -- 2567Akhilesh Jaiswal, Indranil Chakraborty, Amogh Agrawal, Kaushik Roy 0001. 8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing
2568 -- 2574Xizhu Peng, Jinfeng Guo, Qingqing Bao, ZeYu Li, Haoyu Zhuang, He Tang. A Low-Power Low-Cost On-Chip Digital Background Calibration for Pipelined ADCs
2575 -- 2586Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, SinNyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Hiroki Ishikuro, Tetsuro Itakura. Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits
2587 -- 2595Irith Pomeranz. Padding of Multicycle Broadside and Skewed-Load Tests
2596 -- 2607Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras. Postbond Test of Through-Silicon Vias With Resistive Open Defects
2608 -- 2619Wenqing Song, Huayi Zhou, Kai Niu, Zaichen Zhang, Li Li, Xiaohu You, Chuan Zhang. Efficient Successive Cancellation Stack Decoder for Polar Codes
2620 -- 2628Jing Guo 0004, Shanshan Liu, Lei Zhu 0004, Fabrizio Lombardi. A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes
2629 -- 2640Florian Zaruba, Luca Benini. The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology
2641 -- 2654Xin Zhan, Jianhao Chen, Edgar Sánchez-Sinencio, Peng Li 0001. Power Management for Multicore Processors via Heterogeneous Voltage Regulation and Machine Learning Enabled Adaptation
2655 -- 2667Zhengyu Chen, Hai Zhou, Jie Gu. R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction
2668 -- 2679Liang Chang, Xin Ma, Zhaohao Wang, Youguang Zhang, Yuan Xie 0001, Weisheng Zhao. PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks
2680 -- 2692Jackson Melchert, Setareh Behroozi, Jingjie Li, Younghyun Kim. SAADI-EC: A Quality-Configurable Approximate Divider for Energy Efficiency
2693 -- 2697Rahul Kumar, Brajesh Kumar Kaushik, R. Balasubramanian. Multispectral Transmission Map Fusion Method and Architecture for Image Dehazing
2698 -- 2702Yu-Kai Chiu, Shen-Iuan Liu. A PVT-Tolerant MDLL Using a Frequency Calibrator and a Voltage Monitor

Volume 27, Issue 10

2223 -- 2236Xinyi Ge, Yong Chen 0005, Xiaoteng Zhao, Pui-In Mak, Rui P. Martins. Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter
2237 -- 2245Seong-Jin Yun, Jiseong Lee, Yun Chan Im, Yong Sin Kim. A Digital LDO Regulator With a Self-Clocking Burst Logic for Ultralow Power Applications
2246 -- 2259Anindita Paul, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal, José Miguel Rocha-Pérez. Pseudo-Three-Stage Miller Op-Amp With Enhanced Small-Signal and Large-Signal Performance
2260 -- 2271Iman Y. Taha, Mitra Mirhassani. A 24-GHz DCO With High-Amplitude Stabilization and Enhanced Startup Time for Automotive Radar
2272 -- 2283Sadegh Yazdanshenas, Vaughn Betz. The Costs of Confidentiality in Virtualized FPGAs
2284 -- 2295J. Kokila, N. Ramasubramanian, Nagi Naganathan. Resource Efficient Metering Scheme for Protecting SoC FPGA Device and IPs in IoT Applications
2296 -- 2304Shukla Banik, Suchismita Roy, Bibhash Sen. Application-Dependent Testing of FPGA Interconnect Network
2305 -- 2316Umamaheswara Rao Tida, Cheng Zhuo, Yiyu Shi. Single-Inductor-Multiple-Tier Regulation: TSV-Inductor-Based On-Chip Buck Converters for 3-D IC Power Delivery
2317 -- 2330Lennart Bamberg, Alberto García Ortiz. Coding-Based Low-Power Through-Silicon-Via Redundancy Schemes for Heterogeneous 3-D SoCs
2331 -- 2343Saru Vig, Rohan Juneja, Guiyuan Jiang, Siew Kei Lam, Changhai Ou. Framework for Fast Memory Authentication Using Dynamically Skewed Integrity Tree
2344 -- 2353Yajuan He, Jiubai Zhang, Xiaoqing Wu, Xin Si, Shaowei Zhen, Bo Zhang 0027. A Half-Select Disturb-Free 11T SRAM Cell With Built-In Write/Read-Assist Scheme for Ultralow-Voltage Operations
2354 -- 2364Cuiping Shao, Huiyun Li, Jiayan Fang, Qihua Deng. An Error Location and Correction Method for Memory Based on Data Similarity Analysis
2365 -- 2374Hayoung Lee, Donghyun Han, Seungtaek Lee, Sungho Kang. Dynamic Built-In Redundancy Analysis for Memory Repair
2375 -- 2386Fazal Hameed, Jerónimo Castrillón. A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement
2387 -- 2400Wooyoung Jang. Unaligned Burst-Aware Memory Subsystem
2401 -- 2412Ing-Chao Lin, Da-Wei Chang, Chen-Tai Kao, Sheng-Xuan Lin. Infection-Based Dead Page Prediction in Hybrid Memory Architecture
2413 -- 2422Suk Min Kim, Byungkyu Song, Seong-Ook Jung. Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM
2423 -- 2433Hang Wang, Tiancheng Wang, Longjun Liu, Hongbin Sun 0001, Nanning Zheng. Efficient Compression-Based Line Buffer Design for Image/Video Processing Circuits
2434 -- 2446Tai-Cheng Lee, Yih-Lang Li. Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay
2447 -- 2458Kouki Mohamed. Model Order Reduction Method for Large-Scale RC Interconnect and Implementation of Adaptive Digital PI Controller
2459 -- 2463Weiqiang Liu, Sailong Fan, Ayesha Khalid, Ciara Rafferty, Máire O'Neill. Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA
2464 -- 2468Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, Hsiang-Yu Shih. 74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations

Volume 27, Issue 1

1 -- 10Scott Lerner, Baris Taskin. Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis
11 -- 19Ryuichi Enomoto, Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada. A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration
20 -- 28Martin Omaña, Alessandro Fiore, Marco Mongitore, Cecilia Metra. Fault-Tolerant Inverters for Reliable Photovoltaic Systems
29 -- 36Chun-Chi Chen, Chao-Lieh Chen, Yi Lin, Song-Quan You. An All-Digital Time-Domain Smart Temperature Sensor With a Cost-Efficient Curvature Correction
37 -- 46Maryam Rezaei Khezeli, Mohammad Hossein Moaiyeri, Ali Jalali. Comparative Analysis of Simultaneous Switching Noise Effects in MWCNT Bundle and Cu Power Interconnects in CNTFET-Based Ternary Circuits
47 -- 56Pan Xue, Yilei Shen, Dan Fang, Chenyang Wang, Haijun Shao, Ting Yi, Xiaoyang Zeng, Zhiliang Hong. A 2-D Predistortion Based on Profile Inversion for Fully Digital Cartesian Transmitter
57 -- 68Jai-Ming Lin, You-Lun Deng, Szu-Ting Li, Bo-Heng Yu, Li-Yen Chang, Te-Wei Peng. Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles
69 -- 82Ricardo Martins 0003, Nuno Lourenço 0003, Nuno Horta, Jun Yin, Pui-In Mak, Rui P. Martins. Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications
83 -- 91Ned Bingham, Rajit Manohar. QDI Constant-Time Counters
92 -- 102Jiwoong Choi, Boyeal Kim, Hyun Kim, Hyuk-Jae Lee. A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace
103 -- 115Daniel Morrison, Dennis Delic, Mehmet Rasit Yuce, Jean-Michel Redoute. Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications
116 -- 125Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso. Dynamic Partial Reconfiguration of Customized Single-Row Accelerators
126 -- 137Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim. An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175µW/Channel in 65-nm CMOS
138 -- 146Sungju Ryu, Naebeom Park, Jae-Joon Kim. Feedforward-Cutset-Free Pipelined Multiply-Accumulate Unit for the Machine Learning Accelerator
147 -- 158Jae Young Hur. Contiguity Representation in Page Table for Memory Management Units
159 -- 172Xunzhao Yin, Xiaoming Chen, Michael T. Niemier, Xiaobo Sharon Hu. Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits
173 -- 181Jiangtao Xu, Wei Li, Kaiming Nie, Liqiang Han, Xiyang Zhao. A Method to Reduce the Effect on Image Quality Caused by Resistance of Column Bus
182 -- 192Amir Bazrafshan, Mohammad Taherzadeh-Sani, Frederic Nabki. An Analog LO Harmonic Suppression Technique for SDR Receivers
193 -- 204ByongChan Lim, Mark Horowitz. An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification
205 -- 218Xu Fang, Yang Yu, Xiyuan Peng. TSV Prebond Test Method Based on Switched Capacitors
219 -- 228Mi Zhou, Zhuochao Sun, Qiong Wei Low, Liter Siek. Multiloop Control for Fast Transient DC-DC Converter
229 -- 242Longfei Wang, S. Karen Khatamifard, Ulya R. Karpuzcu, Selçuk Köse. Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation
243 -- 247Chenchang Zhan, Guigang Cai, Wing-Hung Ki. A Transient-Enhanced Output-Capacitor-Free Low-Dropout Regulator With Dynamic Miller Compensation
248 -- 252Amandeep Kaur, Deepak Mishra 0003, Mukul Sarkar. A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC