| 1 | -- | 10 | Scott Lerner, Baris Taskin. Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis |
| 11 | -- | 19 | Ryuichi Enomoto, Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada. A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration |
| 20 | -- | 28 | Martin Omaña, Alessandro Fiore, Marco Mongitore, Cecilia Metra. Fault-Tolerant Inverters for Reliable Photovoltaic Systems |
| 29 | -- | 36 | Chun-Chi Chen, Chao-Lieh Chen, Yi Lin, Song-Quan You. An All-Digital Time-Domain Smart Temperature Sensor With a Cost-Efficient Curvature Correction |
| 37 | -- | 46 | Maryam Rezaei Khezeli, Mohammad Hossein Moaiyeri, Ali Jalali. Comparative Analysis of Simultaneous Switching Noise Effects in MWCNT Bundle and Cu Power Interconnects in CNTFET-Based Ternary Circuits |
| 47 | -- | 56 | Pan Xue, Yilei Shen, Dan Fang, Chenyang Wang, Haijun Shao, Ting Yi, Xiaoyang Zeng, Zhiliang Hong. A 2-D Predistortion Based on Profile Inversion for Fully Digital Cartesian Transmitter |
| 57 | -- | 68 | Jai-Ming Lin, You-Lun Deng, Szu-Ting Li, Bo-Heng Yu, Li-Yen Chang, Te-Wei Peng. Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles |
| 69 | -- | 82 | Ricardo Martins 0003, Nuno Lourenço 0003, Nuno Horta, Jun Yin, Pui-In Mak, Rui P. Martins. Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications |
| 83 | -- | 91 | Ned Bingham, Rajit Manohar. QDI Constant-Time Counters |
| 92 | -- | 102 | Jiwoong Choi, Boyeal Kim, Hyun Kim, Hyuk-Jae Lee. A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace |
| 103 | -- | 115 | Daniel Morrison, Dennis Delic, Mehmet Rasit Yuce, Jean-Michel Redoute. Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications |
| 116 | -- | 125 | Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso. Dynamic Partial Reconfiguration of Customized Single-Row Accelerators |
| 126 | -- | 137 | Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim. An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175µW/Channel in 65-nm CMOS |
| 138 | -- | 146 | Sungju Ryu, Naebeom Park, Jae-Joon Kim. Feedforward-Cutset-Free Pipelined Multiply-Accumulate Unit for the Machine Learning Accelerator |
| 147 | -- | 158 | Jae Young Hur. Contiguity Representation in Page Table for Memory Management Units |
| 159 | -- | 172 | Xunzhao Yin, Xiaoming Chen, Michael T. Niemier, Xiaobo Sharon Hu. Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits |
| 173 | -- | 181 | Jiangtao Xu, Wei Li, Kaiming Nie, Liqiang Han, Xiyang Zhao. A Method to Reduce the Effect on Image Quality Caused by Resistance of Column Bus |
| 182 | -- | 192 | Amir Bazrafshan, Mohammad Taherzadeh-Sani, Frederic Nabki. An Analog LO Harmonic Suppression Technique for SDR Receivers |
| 193 | -- | 204 | ByongChan Lim, Mark Horowitz. An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification |
| 205 | -- | 218 | Xu Fang, Yang Yu, Xiyuan Peng. TSV Prebond Test Method Based on Switched Capacitors |
| 219 | -- | 228 | Mi Zhou, Zhuochao Sun, Qiong Wei Low, Liter Siek. Multiloop Control for Fast Transient DC-DC Converter |
| 229 | -- | 242 | Longfei Wang, S. Karen Khatamifard, Ulya R. Karpuzcu, Selçuk Köse. Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation |
| 243 | -- | 247 | Chenchang Zhan, Guigang Cai, Wing-Hung Ki. A Transient-Enhanced Output-Capacitor-Free Low-Dropout Regulator With Dynamic Miller Compensation |
| 248 | -- | 252 | Amandeep Kaur, Deepak Mishra 0003, Mukul Sarkar. A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC |