| 411 | -- | 420 | Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer. A New Static Compaction of Deterministic Test Sets |
| 421 | -- | 430 | Irith Pomeranz. Sharing of Compressed Tests Among Logic Blocks |
| 431 | -- | 441 | Abdullah Ibn Abbas, Xiangdong Jia, Glenn E. R. Cowan. A Power-Proportional, Dual-Bandwidth, and Constant-Delay Receiver Front-End for Energy-Efficient Dual-Rate Optical Links |
| 442 | -- | 455 | Wu Zhou, Yiming Ouyang, Dongyu Xu, Zhengfeng Huang, Huaguo Liang, Xiaoqing Wen. Energy-Efficient Multiple Network-on-Chip Architecture With Bandwidth Expansion |
| 456 | -- | 469 | Jie Chen 0042, Igor Loi, Eric Flamand, Giuseppe Tagliavini, Luca Benini, Davide Rossi. Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters |
| 470 | -- | 483 | Wenhao Sun, Deng Liu, Zhiwei Zou, Wendi Sun, Song Chen 0001, Yi Kang. Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays |
| 484 | -- | 497 | Ming Ling, Qingde Lin, Ruiqi Chen, Haimeng Qi, Mengru Lin, Yanxiang Zhu, Jiansheng Wu. Vina-FPGA: A Hardware-Accelerated Molecular Docking Tool With Fixed-Point Quantization and Low-Level Parallelism |
| 498 | -- | 511 | Jones William Goebel, Luciano Volcan Agostini, Bruno Zatt, Marcelo Schiavon Porto. A High-Throughput Hardware Design for the AV1 Decoder Intraprediction |
| 512 | -- | 521 | Haofan Ding, Haiyan Dai, Xin Hong, Deyan Chen, Junyuan Wu, Jinghu Li, Zhicong Luo. A 10-Gb/s Inductorless Low-Power TIA With a 400-fF Low-Speed Avalanche Photodiode Realized in CMOS Process |
| 522 | -- | 531 | Zhiting Lin, Min Chen, Peng Sun, Xiulong Wu, Qiang Zhao, Wenjuan Lu, Chunyu Peng. High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications |
| 532 | -- | 542 | Aika Kamei, Hideharu Amano, Takuya Kojima, Daiki Yokoyama, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho. A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops |
| 543 | -- | 554 | Shivani Bathla, Vinita Vasudevan. A Framework for Reliability Analysis of Combinational Circuits Using Approximate Bayesian Inference |
| 555 | -- | 566 | Ayesha Siddique, Khaza Anuarul Hoque. Exposing Reliability Degradation and Mitigation in Approximate DNNs Under Permanent Faults |
| 567 | -- | 577 | Yang Ge, Tejinder Singh Sandhu, Dmitri V. Truhachev, Kamal El-Sankary. A Single-TSV and Single-DCDL Approach for Skew Compensation of Multi-Dies Clock Synchronization in 3-D-ICs |
| 578 | -- | 590 | Youngkwang Lee, Donghyun Han, Sungho Kang. TSV Built-In Self-Repair Architecture for Improving the Yield and Reliability of HBM |
| 591 | -- | 595 | Sangwoo Han, Minjung Cho, Gi Lee, Eui-Young Chung. Page Type-Aware Data Migration Technique for Read Disturb Management of NAND Flash Memory |
| 596 | -- | 600 | Pengzhou He, Yazheng Tu, Tianyou Bao, Leonel Sousa, Jiafeng Xie. COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC |
| 601 | -- | 605 | Irith Pomeranz. Test Data Compression for Transparent-Scan Sequences |
| 606 | -- | 610 | Kexu Chen, Di Li 0003, Dongdong Chen, ChangChun Chai. An Improved MOS Self-Biased Ring Amplifier and Modified Auto-Zeroing Scheme |