| 1879 | -- | 1881 | Mircea R. Stan. Editorial Rolling Out the IEEE TVLSI EDICS |
| 1882 | -- | 1895 | Wenbo Guan, XiaoYan Tang, Hongliang Lu, YuMing Zhang, YiMen Zhang. Thermal-Aware Fixed-Outline 3-D IC Floorplanning: An End-to-End Learning-Based Approach |
| 1896 | -- | 1904 | Sankatali Venkateswarlu, Subrat Mishra, Herman Oprins, Bjorn Vermeersch, Moritz Brunion, Jun-Han Han, Mircea R. Stan, Dwaipayan Biswas, Pieter Weckx, Francky Catthoor. Impact of 3-D Integration on Thermal Performance of RISC-V MemPool Multicore SOC |
| 1905 | -- | 1917 | Wenbo Guan, XiaoYan Tang, Hongliang Lu, YuMing Zhang, YiMen Zhang. ATT-TA: A Cooperative Multiagent Deep Reinforcement Learning Approach for TSV Assignment in 3-D ICs |
| 1918 | -- | 1930 | Carlos Manuel Domínguez-Matas, Antonio J. Ginés, Aránzazu Otín, Valentin Gutierrez, Gildas Léger, Eduardo J. Peralías. Behavioral Model for High-Speed SAR ADCs With On-Chip References |
| 1931 | -- | 1938 | Heng Zhang, Ben He, Xuan Guo, DanYu Wu, Xinyu Liu. A 1-GS/s 12-bit Single-Channel Pipelined ADC in 28-nm CMOS With Input-Split Fully Differential Ring Amplifier |
| 1939 | -- | 1949 | Pai-Hsiang Hsu, Yueh-Ru Lee, Chia-Hung Chen, Chung-Chih Hung. A Low-Noise Area-Efficient Column-Parallel ADC With an Input Triplet for a 120-dB High Dynamic Range CMOS Image Sensor |
| 1950 | -- | 1959 | Mahyar Safiallah, Ahmad Reza Danesh, Haoran Pu, Payam Heydari. A Current-Adjusting Auto-Zeroing Technique for DC-Offset and Flicker-Noise Cancellation |
| 1960 | -- | 1969 | Cheng-Yen Lee, Sunil P. Khatri. A Digital Low Dropout (LDO) Voltage Regulator Using Pseudoflash Transistors |
| 1970 | -- | 1979 | Ranran Zhou, Haozhe Wang, Peng Wang, Peter Poechmueller, Yong Wang 0006. A 55-nm Three-Stage Operational Transconductance Amplifier With Single Cascode Miller Compensation for Large Capacitive Loads |
| 1980 | -- | 1993 | Wenzhe Zhao, Guoming Yang, Tian Xia 0008, Fei Chen, Nanning Zheng 0001, Pengju Ren. HIPU: A Hybrid Intelligent Processing Unit With Fine-Grained ISA for Real-Time Deep Neural Network Inference Applications |
| 1994 | -- | 2007 | Pai-Yu Tan, Cheng-Wen Wu. A 40-nm 1.89-pJ/SOP Scalable Convolutional Spiking Neural Network Learning Core With On-Chip Spatiotemporal Back-Propagation |
| 2008 | -- | 2015 | Meenali Janveja, Ashwani Kumar Sharma, Abhyuday Bhardwaj, Jan Pidanic, Gaurav Trivedi. An Optimized Low-Power VLSI Architecture for ECG/VCG Data Compression for IoHT Wearable Device Application |
| 2016 | -- | 2029 | Ngo-Doanh Nguyen, Akram Ben Ahmed, Abderazek Ben Abdallah, Khanh N. Dang. Power-Aware Neuromorphic Architecture With Partial Voltage Scaling 3-D Stacking Synaptic Memory |
| 2030 | -- | 2043 | Yicong Zhang, Mingyu Wang, Yangzhan Mai, Zhiyi Yu. TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs |
| 2044 | -- | 2052 | Hongyang Hu, Xiwei Wang, Zi Wang, Haiyang Zhou, Danian Dong, Jinshan Yue, Wan Pang, Xiaoxin Xu, Chunmeng Dou. A 40-nm SONOS Digital CIM Using Simplified LUT Multiplier and Continuous Sample-Hold Sense Amplifier for AI Edge Inference |
| 2053 | -- | 2060 | Ashvinikumar Dongre, Bipul Boro, Gaurav Trivedi. ADC-Less Reprogrammable RRAM Array Architecture for In-Memory Computing |
| 2061 | -- | 2074 | Dongyu Xu, Yiming Ouyang, Wu Zhou, Zhengfeng Huang, Huaguo Liang, Xiaoqing Wen. RMC_NoC: A Reliable On-Chip Network Architecture With Reconfigurable Multifunctional Channel |
| 2075 | -- | 2088 | Zeinab Seifoori, Behzad Omidi, Hossein Asadi 0001. PERA: Power-Efficient Routing Architecture for SRAM-Based FPGAs in Dark Silicon Era |
| 2089 | -- | 2101 | Jiuxin Gong, Zhaoming Lu, Luhan Wang, Xinghe Chu, Xiangming Wen. A Reusable and Efficient Architecture for QC-LDPC Encoder With Less Expansion Factors |
| 2102 | -- | 2111 | Nan Zhang, Jinghan Feng, Peixin Zhang, Fengkui Gong. Parallel Doubly Fed Symbol Timing Recovery Algorithm and FPGA Implementation for Burst Broadband Satellite Access |
| 2112 | -- | 2125 | Panagiota Papavramidou, Michael Nicolaidis. Reducing Power Dissipation in Memory Repair for High Fault Rates |
| 2126 | -- | 2136 | Xinghua Xue, Cheng Liu 0008, Ying Wang 0001, Bing Yang, Tao Luo 0014, Lei Zhang 0008, Huawei Li 0001, Xiaowei Li 0001. Soft Error Reliability Analysis of Vision Transformers |
| 2137 | -- | 2141 | Sungju Ryu, Youngtaek Oh, Jae-Joon Kim. Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks |
| 2142 | -- | 2146 | Yuyang Li, Yejoong Kim, Inhee Lee. 2, 4.7-μW Convolutional Neural Network Layer Accelerator for Miniature Systems |
| 2147 | -- | 2151 | Xin Zhao, Dengquan Li, Feida Wang, Yi Shen 0007, Shubin Liu, Ruixue Ding, Zhangming Zhu. An 8-bit 1.5-GS/s Voltage-Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC |
| 2152 | -- | 2156 | Seongun Bae, Minseob Lee, Sang-Min Yoo, Jae-Yoon Sim. A Temperature Compensated Ring Oscillator With LC-Based Period Error Detection |