| 1639 | -- | 1652 | Wenbo Guan, XiaoYan Tang, Hongliang Lu, YuMing Zhang, YiMen Zhang. A Novel Thermal-Aware Floorplanning and TSV Assignment With Game Theory for Fixed-Outline 3-D ICs |
| 1653 | -- | 1664 | Wei Xiong, Gang Dong, Changle Zhi, Yang Wang, Zhangming Zhu, Yintang Yang. Miniaturization Strategy for Directional Couplers Based on Through-Silicon Via Insertion and Neuro-Transfer Function Modeling Method |
| 1665 | -- | 1674 | Hamed Aminzadeh, Andrea Ballo, Alfio Dario Grasso, Mohammad Mahdi Valinezhad, Mohammad Jamali. L |
| 1675 | -- | 1685 | R. Malmir, M. B. Ghaznavi-Ghoushchi. Design and Analysis of an Ultralow-Voltage Complementary Fold-Interleaved Multiple-Tail Current Mode Logic |
| 1686 | -- | 1699 | Apostolos Stefanidis, Ioanna Zoumpoulidou, Dionysios Filippas, Giorgos Dimitrakopoulos, Georgios Ch. Sirakoulis. Synthesis of Approximate Parallel-Prefix Adders |
| 1700 | -- | 1712 | Rui Xiao, Yewei Zhang, Bo Wang 0020, Yanfeng Xu, Jicong Fan, Haibin Shen, Kejie Huang. A Low-Power In-Memory Multiplication and Accumulation Array With Modified Radix-4 Input and Canonical Signed Digit Weights |
| 1713 | -- | 1726 | Bruno Sá, Luca Valente, José Martins, Davide Rossi, Luca Benini, Sandro Pinto 0001. CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration |
| 1727 | -- | 1739 | Jianwang Zhai, Yici Cai. Microarchitecture Design Space Exploration via Pareto-Driven Active Learning |
| 1740 | -- | 1753 | Johannes Bund, Matthias Függer, Moti Medina. PALS: Distributed Gradient Clocking on Chip |
| 1754 | -- | 1762 | Irith Pomeranz. Dummy Faulty Units for Reduced Fail Data Volume From Logic Faults |
| 1763 | -- | 1773 | Xinghua Xue, Cheng Liu 0008, Bo Liu 0018, Haitong Huang, Ying Wang 0001, Tao Luo 0014, Lei Zhang, Huawei Li 0001, Xiaowei Li 0001. Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance |
| 1774 | -- | 1787 | Trio Adiono, Rhesa Muhammad Ramadhan, Nana Sutisna, Infall Syafalni, Rahmat Mulyawan, Chang Hong Lin. Fast and Scalable Multicore YOLOv3-Tiny Accelerator Using Input Stationary Systolic Architecture |
| 1788 | -- | 1801 | Haikuo Shao, Jinming Lu, Meiqi Wang, Zhongfeng Wang 0001. An Efficient Training Accelerator for Transformers With Hardware-Algorithm Co-Optimization |
| 1802 | -- | 1815 | Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis. Hidden Costs of Analog Deobfuscation Attacks |
| 1816 | -- | 1825 | Prachi Kashikar, Olivier Sentieys, Sharad Sinha. Lossless Neural Network Model Compression Through Exponent Sharing |
| 1826 | -- | 1838 | Jianwei Xue, Rendong Ying, Faquan Chen, Peilin Liu. SFANC: Scalable and Flexible Architecture for Neuromorphic Computing |
| 1839 | -- | 1851 | Xiangrong Huang, Haikun Jia, Shengnan Dong, Wei Deng 0001, Zhihua Wang 0001, Baoyong Chi. A 24-30-GHz Four-Element Phased Array Transceiver With Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter for 5G Communication |
| 1852 | -- | 1864 | Shao-I Chu, Syuan-An Ke, Sheng-Jung Liu, Yan-Wei Lin. An Efficient Hard-Detection GRAND Decoder for Systematic Linear Block Codes |
| 1865 | -- | 1869 | Jianjun Luo 0003, Hailuan Liu, Ying He, César Vargas Rosales, Lingyan Fan. High-Density NVMe SSD With DRAM-Less eRAID Architecture |
| 1870 | -- | 1873 | Yi Shen 0007, Junyan Hao, Shubin Liu, Zeshuai An, Dengquan Li, Ruixue Ding, Zhangming Zhu. An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain |
| 1874 | -- | 1878 | Jordi Fornt, Pau Fontova-Musté, Martí Caro, Jaume Abella 0001, Francesc Moll, Josep Altet, Christoph Studer. An Energy-Efficient GeMM-Based Convolution Accelerator With On-the-Fly im2col |