| 188 | -- | 198 | David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow. The Transmogrifier-2: a 1 million gate rapid-prototyping system |
| 199 | -- | 211 | Akihiro Tsutsui, Toshiaki Miyazaki. ANT-on-YARDS: FPGA/MPU hybrid architecture for telecommunication data processing |
| 212 | -- | 221 | John Lach, William H. Mangione-Smith, Miodrag Potkonjak. Low overhead fault-tolerant FPGA systems |
| 222 | -- | 231 | R. Glenn Wood, Rob A. Rutenbar. FPGA routing and routability estimation via Boolean satisfiability |
| 232 | -- | 237 | Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses. Some experiments about wave pipelining on FPGA s |
| 238 | -- | 246 | Brian Von Herzen. Signal processing at 250 MHz using high-performance FPGA s |
| 247 | -- | 256 | Michael J. Wirthlin, Brad L. Hutchings. Improving functional density using run-time circuit reconfiguration [FPGAs] |
| 257 | -- | 265 | Moritoshi Yasunaga, I. Hachiya, K. Moki, Jung Hwan Kim. Fault-tolerant self-organizing map implemented by wafer-scale integration |
| 266 | -- | 275 | William Fornaciari, P. Gubian, Donatella Sciuto, Cristina Silvano. Power estimation of embedded systems: a hardware/software codesign approach |
| 276 | -- | 283 | Wei-Kang Huang, Fred J. Meyer, Xiao-Tao Chen, Fabrizio Lombardi. Testing configurable LUT-based FPGA s |
| 284 | -- | 291 | Klaus Herrmann, Jan Otterstedt, H. Jeschke, M. Kuboschek. A MIMD-based video signal processing architecture suitable for large area integration and a 16.6-cm:::2::: monolithic implementation |
| 292 | -- | 298 | Luca Breveglieri, Luigi Dadda. A VLSI inner product macrocell |
| 299 | -- | 308 | Uming Ko, Poras T. Balsara, Ashwini K. Nanda. Energy optimization of multilevel cache architectures for RISC and CISC processors |
| 309 | -- | 313 | Krishnendu Chakrabarty, John P. Hayes. Zero-aliasing space compaction of test responses using multiple parity signatures |
| 314 | -- | 322 | Lei Wang, José Pineda de Gyvez, Edgar Sánchez-Sinencio. Time multiplexed color image processing based on a CNN with cell-state outputs |
| 323 | -- | 331 | S. Bose, P. Agrawal, V. D. Agrawal. A rated-clock test method for path delay faults |
| 332 | -- | 342 | S. Bose, P. Agrawal. Concurrent fault simulation on message passing multicomputers |