| 4 | -- | 5 | Pinaki Mazumder. Guest Editorial Special Section On Impacts Of Emerging Technologies On VLSI Systems |
| 6 | -- | 17 | Andreas Thiede, Zhi-Gong Wang, Michael Schlechtweg, M. Lang, P. Leber, Zhihao Lao, Ulrich Nowotny, V. Hurm, M. Rieger-Motzer, M. Ludwig, M. Sedler, K. Kohler, W. Bronner, J. Hornung, A. Hulsmann, G. Kaufel, B. Raynor, J. Schneider, T. Jakobus, J. Schroth, Manfred Berroth. Mixed signal integrated circuits based on GaAs HEMTs |
| 18 | -- | 30 | Roberto Sarmiento, V. de Armas, José Francisco López, Juan A. Montiel-Nelson, Antonio Núñez. A CORDIC processor for FFT computation and its implementation using gallium arsenide technology |
| 31 | -- | 38 | Terry J. Fountain, Michael J. B. Duff, D. G. Crawley, C. D. Tomlinson, C. D. Moffat. The use of nanoelectronic devices in highly parallel computing systems |
| 39 | -- | 42 | H. Okazaki, T. Nakagawa, M. Muraguchi, H. Fukuyama, K. Maezawa, Masafumi Yamamoto. Sampling phase detector using a resonant tunneling high electron mobility transistor for microwave phase-locked oscillators |
| 43 | -- | 46 | M. Fujii, K. Numata, T. Maeda, M. Tokushima, S. Wada, M. Fukaishi, M. Ishikawa. A 150 mW 8: 1 MUX and a 170 mW 1: 8 DEMUX for 2.4 gb/s optical-fiber communication systems using n-AlGaAs/i-InGaAs HJFET s |
| 47 | -- | 51 | Richard B. Brown, Bruce Bernhardt, M. LaMacchia, J. Abrokwah, Phiroze N. Parakh, Todd D. Basso, Spencer M. Gold, S. Stetson, Claude R. Gauthier, D. Foster, B. Crawforth, T. McQuire, Karem A. Sakallah, Ronald J. Lomax, Trevor N. Mudge. Overview of complementary GaAs technology for high-speed VLSI circuits |
| 52 | -- | 55 | Pete M. Campbell, Hans J. Greub, Atul Garg, A. Steidl, Steven R. Carlough, Matthew W. Ernest, Robert F. Philhower, Cliff A. Maier, Russell P. Kraft, John F. McDonald. A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT s |
| 56 | -- | 65 | Luis A. Plana, Steven M. Nowick. Architectural optimization for low-power nonpipelined asynchronous systems |
| 65 | -- | 73 | Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang. Statistical estimation of average power dissipation using nonparametric techniques |
| 74 | -- | 83 | Naresh Maheshwari, Sachin S. Sapatnekar. Efficient retiming of large circuits |
| 84 | -- | 100 | Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong. SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design |
| 101 | -- | 113 | S. K. Jain, Leilei Song, Keshab K. Parhi. Efficient semisystolic architectures for finite-field arithmetic |
| 114 | -- | 121 | M. Aberbour, A. Houelle, Habib Mehrez, N. Vaucher, Alain Guyot. On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard |
| 122 | -- | 133 | Bapiraju Vinnakota, Jason Andrews. Fast fault translation |
| 134 | -- | 140 | Chuan-Yu Wang, Kaushik Roy. Maximum power estimation for CMOS circuits using deterministic and statistical approaches |
| 141 | -- | 149 | Stuart F. Oberman, Michael J. Flynn. Minimizing the complexity of SRT tables |
| 150 | -- | 157 | L. K. John, E. John. A dynamically reconfigurable interconnect for array processors |
| 158 | -- | 167 | Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey. Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC s |
| 168 | -- | 172 | Arvind Srinivasan, G. D. Huber, David P. LaPotin. Accurate area and delay estimation from RTL descriptions |
| 173 | -- | 176 | Elisardo Antelo, Montserrat Bóo, Javier D. Bruguera, Emilio L. Zapata. A novel design of a two operand normalization circuit |
| 176 | -- | 180 | Paul G. Ryan, W. Kent Fuchs. Dynamic fault dictionaries and two-stage fault isolation |