| 131 | -- | 141 | C. P. Ravikumar, Hemant Joshi. SCOAP-based Testability Analysis from Hierarchical Netlists |
| 143 | -- | 150 | Vincenzo Acciaro, Amiya R. Nayak. Characterization of Catastrophic Faults in Reconfigurable Systolic Arrays |
| 151 | -- | 161 | Fadi Busaba, Parag K. Lala, Alvernon Walker. On Self-Checking Design of CMOS Circuits for Multiple Faults |
| 163 | -- | 176 | Gerald Spiegel, Albrecht P. Stroele. Realistic Fault Modeling and Extraction of Multiple Bridging and Break Faults |
| 177 | -- | 189 | Ioannis Karafyllidis, Ioannis Andreadis, Philippos G. Tsalides, Adonios Thanailakis. Non-linear Hybrid Cellular Automata as Pseudorandom Pattern Generators for VLSI Systems |
| 191 | -- | 201 | Sunil R. Das, Nita Goel, Wen-Ben Jone, Amiya R. Nayak. Syndrome Signature in Output Compaction for VLSI Built-in Self-Test |
| 203 | -- | 210 | Ioannis Andreadis, I. Kokolakis, Antonios Gasteratos, Philippos G. Tsalides. A Stochastic D/A Converter Based on a Cellular Automaton Architecture |
| 211 | -- | 224 | Dimitrios Karayiannis, Spyros Tragoudas. Timing-Driven Circuit Implementation |