| 291 | -- | 317 | Kostas Masselos, Koen Danckaert, Francky Catthoor, Nikolaos D. Zervas, Constantinos E. Goutis, Hugo De Man. A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints |
| 319 | -- | 332 | Hao-Chieh Chang, Jiun-Ying Jiu, Li-Lin Chen, Liang-Gee Chen. A Low Power 8 x 8 Direct 2-D DCT Chip Design |
| 333 | -- | 359 | S. Ramanathan, S. K. Nandy, V. Visvanathan. Reconfigurable Filter Coprocessor Architecture for DSP Applications |
| 361 | -- | 368 | Kiamal Z. Pekmestzi, Paraskevas Kalivas. Constant Number Serial Pipeline Multipliers |
| 369 | -- | 381 | Ming-Bo Lin. A Hardware Architecture for the LZW Compression and Decompression Algorithms Based on Parallel Dictionaries |
| 383 | -- | 396 | Vera P. Behar, Christo A. Kabakchiev, Lyubka Doukovska. Adaptive CFAR PI Processor for Radar Target Detection in Pulse Jamming |
| 397 | -- | 409 | Jin-Shiuh Taur, Chin-Wang Tao. A New Neuro-Fuzzy Classifier with Application to On-Line Face Detection and Recognition |