| 87 | -- | 88 | Wayne P. Burleson, Konstantinos Konstantinides. Guest Editors Introduction |
| 89 | -- | 109 | Lode Nachtergaele, Dennis Moolenaar, Bart Vanhoof, Francky Catthoor, Hugo De Man. System-Level Power Optimization of Video Codecs on Embedded Cores: A Systematic Approach |
| 111 | -- | 123 | Sissades Tongsima, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Nelson L. Passos. Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling |
| 125 | -- | 140 | Jimmy C. Limqueco, Magdy A. Bayoumi. A Vlsi Architecture for Separable 2-D Discrete Wavelet Transform |
| 141 | -- | 154 | Bongjin Jung, Wayne P. Burleson. Vlsi Array Architectures for Pyramid Vector Quantization |
| 155 | -- | 165 | Edgar Holmann, Toyohiko Yoshida, Akira Yamada, Shin-ichi Uramoto. Single Chip Dual-Issue RISC Processor for Real-Time MPEG-2 Software Decoding |
| 167 | -- | 175 | Takehiro Kamada, Toshihiko Fukuoka, Yuji Nakai, Yoshihiko Fukumoto, Yasuhiro Nakakura, Katsuhiko Ueda, Tomonori Shiomi, Kazuhiro Ota. An Area-Effective Cell-Based Channel Decoder LSI For a Digital Satellite TV Broadcasting |
| 177 | -- | 186 | Ingrid Verbauwhede, Mihran Touriguian. A Low Power DSP Engine for Wireless Communications |
| 187 | -- | 197 | Patrick Schaumont, Serge Vernalde, Marc Engels, Ivo Bolsens. Low Power Digital Frequency Conversion Architectures |