An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems - researchr publication

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Ankur Agiwal, Montek Singh. An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems. In 2005 International Conference on Computer-Aided Design (ICCAD 05), November 6-10, 2005, San Jose, CA, USA. pages 1006-1013, IEEE Computer Society, 2005.

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