The following publications are possibly variants of this publication:
- Silicide Optimization for Electrostatic Discharge Protection Devices in Sub-100 nm CMOS Circuit DesignJam Wem Lee, Yiming Li, Howard Tang. vlsi 2003: 251-260
- Novel fully silicided ballasting and MFT design techniques for ESD protection in advanced deep sub-micron CMOS technologiesKoen G. Verhaege, Christian C. Russ. mr, 41(11):1739-1749, 2001. [doi]
- Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implantD. Alvarez, M. J. Abou-Khalil, C. Russ, Kiran V. Chatty, Robert Gauthier, D. Kontos, J. Li, C. Seguin, R. Halbach. mr, 46(9-11):1597-1602, 2006. [doi]