Table of Contents

• A Reconfigurable Switch for a DSP ArrayFred L. Anderson IV, José G. Delgado-Frias. 3-6
• A Branch File for a Configurable DSP CoreChristian Panis, Gunther Laure, Wolfgang Lazian, Herbert Grünbacher, Jari Nurmi. 7-12
• MPEG-4 HVXC Real-Time Implementation on Floating Point DSPHoon Na, Dae-Gwon Jeong. 13-20
• A Two-Level Reconfigurable Architecture for Digital Signal ProcessingMitchell J. Myjak, José G. Delgado-Frias. 21-27
• Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic DevicesDeshanand P. Singh, Terry P. Borer, Stephen Dean Brown. 28-33
• Bio-Inspired Reconfigurable Architecture for Reliable SystemsX. Zhang, Gabriel Dragffy, Anthony G. Pipe. 34-40
• An Area-Efficient Timing Closure Technique for FPGAs Using Shannon s ExpansionDeshanand P. Singh, Stephen Dean Brown. 41-50
• Fault Tolerance for Multiprocessor Systems Via Time Redundant Task SchedulingHussain Al-Asaad, Alireza Sarvi. 51-57
• A Fault-Tolerant Memory-Based Cell for a Reconfigurable DSP ProcessorDaniel R. Blum, José G. Delgado-Frias. 58-64
• A Study on Fault-Tolerant Circuits Using RedundancyJie Han, Pieter Jonker. 65-69
• Reuse of Firmware Tests in System-On-Chip Design VerificationRobert Chun, Linda Yang. 70-78
• A Low-Voltage Low-Power Digital-Audio Sigma-Delta Modulator in 0.18-µm CMOSJiyi Gu, Majid Ahmadi, William C. Miller. 79-82
• Lower Power Processor Design IssuesAnilkumar Patro, Ashish Mishra. 83-86
• A New Power Efficient Fully Differential Low-Voltage Two Stage OP-AMP ArchitectureJaime Ramírez-Angulo, Shanta Thoutam, Gladys Omayra Ducoudray, Ramón González Carvajal. 87-91
• A Power-Efficient Level Converter Design For Multi-Supply Voltage CMOS Analog Integrated CircuitsNaresh Sarwabhotla, Arthi Kothandaraman. 92-96
• Models for Full-Chip Power Dissipation in Field Programmable Gate Arrays and the Impact of Subthreshold Leakage CurrentArifur Rahman. 97-106
• Cross Reduction for Orthogonal Circuit VisualizationThomas Eschbach, Wolfgang Günther, Bernd Becker. 107-113
• Switching Windows Computation in Presence of Crosstalk NoiseJanet Meiling Wang, Pinhong Chen, Omar Hafiz. 114-118
• Channel Routing with Crosstalk ConsiderationNathaniel Bird, Ethan S. Miller, Paul J. Pfeiffer, Srinivasa Vemuru. 119-124
• Energy Efficient and Noise-Tolerant XOR-XNOR Circuit DesignSumeer Goel, Mohamed A. Elgamel, Magdy A. Bayoumi. 125-130
• An Area-Efficient Bit-Serial Integer MultiplierManfred Schimmler, Bertil Schmidt, Hans-Werner Lang, Sven Heithecker. 131-137
• Planar Spiral Inductor Modeling for RFIC DesignAli Telli, Simsek Demir, Murat Askar. 138-142
• Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion StrategyScott C. Smith. 143-149
• High-Resolution WTA-MAX Circuit for Large NetworksVolnei A. Pedroni. 150-154
• A Novel Smart Power ASIC (SPIC) for Integrated Control of Cascaded Power ConvertersAdnan M. Lokhandwala, Sudip K. Mazumder. 155-161
• An Improved Circuit Design for Parallel Sequence GenerationYoungsoo Kim, Janghong Yoon, Sungok Kim. 162-165
• A Low Voltage Micropower 16-Word by 16-Bit 3-Port Asynchronous Register FileKhia-Ho Chang, Bah-Hwee Gwee, Joseph Sylvester Chang. 166-172
• Level Shifter Circuit Having Dual Outputs for FPD Gate DriverYil Suk Yang, Jongdae Kim, Tae Moon Roh, Dae Wood Lee, Sung-Ku Kwon, Il-Yong Park, Byoung Gon Yu. 173-177
• Design and Characterization of NULL Convention Arithmetic Logic UnitsSatish K. Bandapati, Scott C. Smith. 178-184
• A Study on the 8bit Pipeline RISC ProcessorKang Hyeon Rhee. 185-189
• Multithreaded parallel VLSI Leaf Cell Generator Using Agents 2Evandro de Araújo Jardini, Dilvan de Abreu Moreira. 190-196
• Foundation of Quantum CapacityNoboru Watanabe. 197-202
• Reducing the Hitting and the Cover Times of Random Walks on Finite Graphs by Local Topological InformationSatoshi Ikeda, Izumi Kubo, Masafumi Yamashita. 203-207
• A Stochastic Limit Approach to the SAT ProblemLuigi Accardi, Masanori Ohya. 208-216
• Quantum Search Algorithm for Automated Test Pattern Generation in VLSI TestingAmardeep Singh. 217-223
• On-Line Location of Multiple Faults in LUT Based Reconfigurable SystemsL. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti, Sivaprakasam Suresh. 224-232
• Intelligent Device Parameter Extraction for Nanoscale MOSFETs EraYiming Li, Shao-Ming Yu, Hsiao-Mei Lu. 233-239
• Properties of A1/BaTa2O6/GaN MIS StructureJ. K. Kim, S. H. Won, Ki-Seok Chung, H. D. Cho, T. W. Kang, T. S. Nam, C. S. Kang, C. H. Yi, D. S. Kim. 240-243
• Quantum Mechanical Gate Current Simulation in MOSFETs with Ultrathin OxidesShih-Ching Lo, Jyun-Hwei Tsai, Jer-Ming Hsu, Yiming Li. 244-250
• Silicide Optimization for Electrostatic Discharge Protection Devices in Sub-100 nm CMOS Circuit DesignJam Wem Lee, Yiming Li, Howard Tang. 251-260
• Applying Stochastic Modeling to Bus Arbitration for Network-On-Chip SystemsSankalp Kallakuri, Alex Doboli, Simona Doboli. 261-265
• A Compressed Page Management Scheme for NAND-Type Flash MemoryKeun Soo Yim, Kern Koh, Hyokyung Bahn. 266-271
• Scheduling and Optimal Voltage Selection with Multiple Supply Voltages under Resource ConstraintsLing Wang, Yingtao Jiang, Henry Selvaraj. 272-278
• Universal Reed-Solomon Decoder Using Hardware/Software Co-Design MethodSeung Wook Lee, Jong-Tae Kim. 279-284
• A Simple Circuit to Reduce the Search Range for Large Prime NumbersManfred Schimmler, Viktor Bunimov. 285-291
• A Genetic Algorithm for Restricted Cases of the Rectilinear Steiner Problem with ObstaclesRita M. Hare, Bryant A. Julstrom. 292-297
• Learning Annealing Schedules for Channel RoutingTodd W. Neller, David C. Hettlinger. 298-302
• Size of Quantum Versus Deterministic Finite AutomataAndris Ambainis, Uldis Barbans, Agnese Belousova, Aleksandrs Belovs, Ilze Dzelme, Girts Folkmanis, Rusins Freivalds, Peteris Ledins, Rihards Opmanis, Agnis Skuskovniks. 303-308
• Lower Bounds for Query Complexity of Some Graph ProblemsLelde Lace, Rusins Freivalds. 309-316
• SEBSW-2: SEcret-Key Block Cipher SWitcherHirotsuga Kajisaki, Takakazu Kurokawa. 317-323
• The Design and Analysis of an Elliptic Curve CryptosystemGene Eu Jan, Chiou-Min Shen, Shao-Wei Leu, Cheng-Hung Li. 324-328
• The Design and Implementation of a 2048-Bit RSA Encryption/Decryption ChipGene Eu Jan, Lokar J. Y. Lin, W. R. Liou, Y. Y. Chen. 329-338
• A Feed-Forward Time-Multiplexed Neural Network with Mixed-Signal Neuron-Synapse ArraysMitra Mirhassani, Majid Ahmadi, William C. Miller. 339-344
• Highly Linear Wide Input Range CMOS OTA Architectures Operating in Subthreshold and Strong InversionJaime Ramírez-Angulo, Chandrika Durbha, Gladys Omayra Ducoudray, Ramón González Carvajal. 345-350
• Phase Coincidence Technique for Frequency Difference MeasurementBhupen P. Zaveri. 351-355
• PEDE (Plasma Edge Damage Effect) Curing by Various Heat TreatmentJae-Young Yi, Yong-Hui Lee, Cheon-Hee Yi. 356-360
• A High Speed Efficient N x N Bit Multiplier Based on Ancient Indian Vedic MathematicsVishal Verma, Himanshu Thapliyal. 361-365
• High Speed, Small Area AES Block Cipher Coprocessor Design for USIM CardYunKyung Lee, Youngsu Park. 366-372
• Simultaneous Switching Noise Estimation Including the Effects of the Driving Transistor Gate-Source CapacitanceSrinivasa Vemuru. 373-378
• The Advanced Encryption Standard on an Asynchronous Shared-Memory MultiprocessorScott F. Smith 0002. 379-381
• Derving Intermediary RTLs for Verification of Pipelined Synthesized DesignsSuleyman Tosun, Hakduran Koc, Nazanin Mansouri. 382