A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Igor Arsovski, Travis Hebig, Daniel Dobson, Reid Wistort. A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation. J. Solid-State Circuits, 48(4):932-939, 2013. [doi]

This author has not been identified. Look up 'Igor Arsovski' in GoogleThis author has not been identified. Look up 'Travis Hebig' in GoogleThis author has not been identified. Look up 'Daniel Dobson' in GoogleThis author has not been identified. Look up 'Reid Wistort' in Google

runs on WebDSL