Igor Arsovski, Travis Hebig, Daniel Dobson, Reid Wistort. A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation. J. Solid-State Circuits, 48(4):932-939, 2013. [doi]
@article{ArsovskiHDW13,
title = {A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation},
author = {Igor Arsovski and Travis Hebig and Daniel Dobson and Reid Wistort},
year = {2013},
doi = {10.1109/JSSC.2013.2239092},
url = {http://dx.doi.org/10.1109/JSSC.2013.2239092},
researchr = {https://researchr.org/publication/ArsovskiHDW13},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {48},
number = {4},
pages = {932-939},
}