T. Huynh Bao, Dmitry Yakimets, Julien Ryckaert, Ivan Ciofi, R. Baert, A. Veloso, J. Bommels, Nadine Collaert, Philippe Roussel, S. Demuynck, Praveen Raghavan, Abdelkarim Mercha, Zsolt Tokei, Diederik Verkest, Aaron Thean, Piet Wambacq. Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. In 44th European Solid State Device Research Conference, ESSDERC 2014, Venice Lido, Italy, September 22-26, 2014. pages 102-105, IEEE, 2014. [doi]
@inproceedings{BaoYRCBVBCRDRMTVTW14,
title = {Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies},
author = {T. Huynh Bao and Dmitry Yakimets and Julien Ryckaert and Ivan Ciofi and R. Baert and A. Veloso and J. Bommels and Nadine Collaert and Philippe Roussel and S. Demuynck and Praveen Raghavan and Abdelkarim Mercha and Zsolt Tokei and Diederik Verkest and Aaron Thean and Piet Wambacq},
year = {2014},
doi = {10.1109/ESSDERC.2014.6948768},
url = {http://dx.doi.org/10.1109/ESSDERC.2014.6948768},
researchr = {https://researchr.org/publication/BaoYRCBVBCRDRMTVTW14},
cites = {0},
citedby = {0},
pages = {102-105},
booktitle = {44th European Solid State Device Research Conference, ESSDERC 2014, Venice Lido, Italy, September 22-26, 2014},
publisher = {IEEE},
isbn = {978-1-4799-4378-4},
}