A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache - researchr publication authors

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John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael Sperling, Abraham Mathews, William R. Reohr, Kavita Nair, N. Cao. A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache. In IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010. pages 342-343, IEEE, 2010. [doi]

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