The following publications are possibly variants of this publication:
- A 45 nm SOI Embedded DRAM Macro for the POWERâ„¢ Processor 32 MByte On-Chip L3 CacheJohn Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Caon. jssc, 46(1):64-75, 2011. [doi]
- Isolated Preset Architecture for a 32nm SOI embedded DRAM macroJohn Barth, Don Plass, Adis Vehabovic, Rajiv V. Joshi, Rouwaida Kanj, Steven Burns, Todd Weaver. vlsic 2012: 110-111 [doi]
- An on-chip dual supply charge pump system for 45nm PD SOI eDRAMJente B. Kuang, A. Mathews, J. Barth, Fadi H. Gebara, T. Nguyen, Jeremy D. Schaub, Kevin J. Nowka, Gary D. Carpenter, Don Plass, E. Nelson, Ivan Vo, William R. Reohr, Toshiaki Kirihata. esscirc 2008: 66-69 [doi]
- A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense AmplifierJohn Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer. isscc 2007: 486-617 [doi]