John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael Sperling, Abraham Mathews, William R. Reohr, Kavita Nair, N. Cao. A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache. In IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010. pages 342-343, IEEE, 2010. [doi]
@inproceedings{BarthPNHFSMRNC10,
title = {A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache},
author = {John Barth and Don Plass and Erik Nelson and Charlie Hwang and Gregory Fredeman and Michael Sperling and Abraham Mathews and William R. Reohr and Kavita Nair and N. Cao},
year = {2010},
doi = {10.1109/ISSCC.2010.5433814},
url = {http://dx.doi.org/10.1109/ISSCC.2010.5433814},
researchr = {https://researchr.org/publication/BarthPNHFSMRNC10},
cites = {0},
citedby = {0},
pages = {342-343},
booktitle = {IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010},
publisher = {IEEE},
isbn = {978-1-4244-6033-5},
}