Sebastien Bilavarn, Guy Gogniat, Jean Luc Philippe, Lilian Bossuet. Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations. IEEE Trans. on CAD of Integrated Circuits and Systems, 25(10):1950-1968, 2006. [doi]
@article{BilavarnGPB06,
title = {Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations},
author = {Sebastien Bilavarn and Guy Gogniat and Jean Luc Philippe and Lilian Bossuet},
year = {2006},
doi = {10.1109/TCAD.2005.862742},
url = {http://doi.ieeecomputersociety.org/10.1109/TCAD.2005.862742},
tags = {design},
researchr = {https://researchr.org/publication/BilavarnGPB06},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {25},
number = {10},
pages = {1950-1968},
}