Harijot Singh Bindra, Chris E. Lokin, Daniël Schinkel, Anne-Johan Annema, Bram Nauta. A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise. J. Solid-State Circuits, 53(7):1902-1912, 2018. [doi]
@article{BindraLSAN18,
title = {A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise},
author = {Harijot Singh Bindra and Chris E. Lokin and Daniël Schinkel and Anne-Johan Annema and Bram Nauta},
year = {2018},
doi = {10.1109/JSSC.2018.2820147},
url = {https://doi.org/10.1109/JSSC.2018.2820147},
researchr = {https://researchr.org/publication/BindraLSAN18},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {53},
number = {7},
pages = {1902-1912},
}