A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise - researchr publication related

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Harijot Singh Bindra, Chris E. Lokin, Daniël Schinkel, Anne-Johan Annema, Bram Nauta. A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise. J. Solid-State Circuits, 53(7):1902-1912, 2018. [doi]

The following publications are possibly variants of this publication:

A 174μVRMS Input Noise, 1 G8/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the LatchHarijot Singh Bindra, Jeroen Ponte, Bram Nauta. isscc 2022: 1-3 [doi]

A 1.2-V 10-μ W NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2°C (3 Sigma ) From - 70°C to 125°CFabio Sebastiano, Lucien J. Breems, Kofi A. A. Makinwa, Salvatore Drago, Domine Leenaerts, Bram Nauta. jssc, 45(12):2591-2601, 2010. [doi]

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