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Jean Paul Caisso, Eduard Cerny, Nicholas C. Rumin. A recursive technique for computing delays in series-parallel MOS transistor circuits. IEEE Trans. on CAD of Integrated Circuits and Systems, 10(5):589-595, 1991. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Transistor-level estimation of worst-case delays in MOS VLSI circuitsMichel Dagenais, Serge Gaiotti, Nicholas C. Rumin. tcad, 11(3):384-395, 1992. [doi]
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