Jonathan Chang, Stefan Rusu, Jonathan Shoemaker, Simon Tam 0001, Ming Huang, Mizan Haque, Siufu Chiu, Kevin Truong, Mesbah Karim, Gloria Leong, Kiran Desai, Richard Goe, Sandhya Kulkarni. A 130-nm triple-V/sub t/ 9-MB third-level on-die cache for the 1.7-GHz Itanium/spl reg/ 2 processor. J. Solid-State Circuits, 40(1):195-203, 2005. [doi]
@article{ChangRSTHHCTKLD05,
title = {A 130-nm triple-V/sub t/ 9-MB third-level on-die cache for the 1.7-GHz Itanium/spl reg/ 2 processor},
author = {Jonathan Chang and Stefan Rusu and Jonathan Shoemaker and Simon Tam 0001 and Ming Huang and Mizan Haque and Siufu Chiu and Kevin Truong and Mesbah Karim and Gloria Leong and Kiran Desai and Richard Goe and Sandhya Kulkarni},
year = {2005},
doi = {10.1109/JSSC.2004.837970},
url = {https://doi.org/10.1109/JSSC.2004.837970},
researchr = {https://researchr.org/publication/ChangRSTHHCTKLD05},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {40},
number = {1},
pages = {195-203},
}