A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs

Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi. A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs. In Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA. pages 1108-1117, IEEE, 2004. [doi]

@inproceedings{ChatterjeeSK04:2,
  title = {A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs},
  author = {Bhaskar Chatterjee and Manoj Sachdev and Ali Keshavarzi},
  year = {2004},
  doi = {10.1109/ITC.2004.10},
  url = {http://doi.ieeecomputersociety.org/10.1109/ITC.2004.10},
  tags = {testing, diagnostics},
  researchr = {https://researchr.org/publication/ChatterjeeSK04%3A2},
  cites = {0},
  citedby = {0},
  pages = {1108-1117},
  booktitle = {Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA},
  publisher = {IEEE},
  isbn = {0-7803-8581-0},
}