Harry I. A. Chen, Edward K. W. Loo, James B. Kuo, Marek Syrzycki. Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS. In Nadine Azémard, Lars J. Svensson, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings. Volume 4644 of Lecture Notes in Computer Science, pages 453-462, Springer, 2007.
Abstract is missing.