Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS - researchr publication related

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Harry I. A. Chen, Edward K. W. Loo, James B. Kuo, Marek Syrzycki. Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS. In Nadine Azémard, Lars J. Svensson, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings. Volume 4644 of Lecture Notes in Computer Science, pages 453-462, Springer, 2007. [doi]

The following publications are possibly variants of this publication:

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process VariationsKumar Yelamarthi, Chien-In Henry Chen. vlsi, 2010, 2010. [doi]

On Mixed PTL/Static Logic for Low-power and High-speed CircuitsGeun Rae Cho, Tom Chen. vlsi, 2001(3):399-406, 2001. [doi]

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