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Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits

Tsai-Chieh Chen, Chia-Cheng Pai, Yi-Zhan Hsieh, Hsiao-Yin Tseng, Chien-Mo James Li, Tsung-Te Liu, I-Wei Chiu. Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits. J. Electronic Testing, 37(4):453-471, 2021. [doi]

Authors

Tsai-Chieh Chen

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Chia-Cheng Pai

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Yi-Zhan Hsieh

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Hsiao-Yin Tseng

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Chien-Mo James Li

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Tsung-Te Liu

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I-Wei Chiu

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