Tsai-Chieh Chen, Chia-Cheng Pai, Yi-Zhan Hsieh, Hsiao-Yin Tseng, Chien-Mo James Li, Tsung-Te Liu, I-Wei Chiu. Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits. J. Electronic Testing, 37(4):453-471, 2021. [doi]
@article{ChenPHTLLC21,
title = {Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits},
author = {Tsai-Chieh Chen and Chia-Cheng Pai and Yi-Zhan Hsieh and Hsiao-Yin Tseng and Chien-Mo James Li and Tsung-Te Liu and I-Wei Chiu},
year = {2021},
doi = {10.1007/s10836-021-05963-z},
url = {https://doi.org/10.1007/s10836-021-05963-z},
researchr = {https://researchr.org/publication/ChenPHTLLC21},
cites = {0},
citedby = {0},
journal = {J. Electronic Testing},
volume = {37},
number = {4},
pages = {453-471},
}