The following publications are possibly variants of this publication:
- A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOSLiangxiao Tang, Weixin Gai, Chih-Kong Ken Yang, Bingyi Ye, Congcong Chen. iscas 2021: 1-4 [doi]
- A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOSDengjie Wang, Ziqiang Wang, Hao Xu, Jiawei Wang, Zeliang Zhao, Chun Zhang, Zhihua Wang 0001, Hong Chen 0002. tcasI, 69(3):1027-1040, 2022. [doi]
- A 125 mW 8.5-11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOSBharath Raghavan, Aida Varzaghani, Lakshmi P. Rao, Henry Park, Xiaochen Yang, Zhi Huang, Yu Chen, Rama Kattamuri, Chunhui Wu, Bo Zhang, Jun Cao, Afshin Momtaz, Namik Kocaman. vlsic 2016: 1-2 [doi]
- A 3.8 mW/Gbps quad-channel 8.5-13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOSTamer Ali, Lakshmi Rao, Ullas Singh, Mohammed M. Abdul-Latif, Yang Liu, Amr Amin Hafez, Henry Park, Anand Vasani, Zhi Huang, Arvindh Iyer, Bo Zhang, Afshin Momtaz, Namik Kocaman. vlsic 2015: 348 [doi]