Combined instruction and loop parallelism in array synthesis for FPGAs

Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay. Combined instruction and loop parallelism in array synthesis for FPGAs. In ISSS. pages 165-170, 2001.

Authors

Steven Derrien

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Sanjay V. Rajopadhye

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Susmita Sur-Kolay

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