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Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay. Combined instruction and loop parallelism in array synthesis for FPGAs. In ISSS. pages 165-170, 2001.
Possibly Related PublicationsThe following publications are possibly variants of this publication: Combining Instruction and Loop Level Parallelism for FPGAsSteven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay. fccm 2001: 273-282 [doi]
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