Combined instruction and loop parallelism in array synthesis for FPGAs

Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay. Combined instruction and loop parallelism in array synthesis for FPGAs. In ISSS. pages 165-170, 2001.

@inproceedings{DerrienRS01,
  title = {Combined instruction and loop parallelism in array synthesis for FPGAs},
  author = {Steven Derrien and Sanjay V. Rajopadhye and Susmita Sur-Kolay},
  year = {2001},
  researchr = {https://researchr.org/publication/DerrienRS01},
  cites = {0},
  citedby = {0},
  pages = {165-170},
  booktitle = {ISSS},
}