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Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh. Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance. IEEE Trans. VLSI Syst., 14(5):514-524, 2006. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Soft-Error Tolerance Analysis and Optimization of Nanometer CircuitsYuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee. date 2005: 288-293 [doi] Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS CircuitsYuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra. iolts 2005: 35-40 [doi]
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