Table of Contents

• Welcome [doi]
• Program Committee [doi]
• IEEE Computer Society TTTC: Test Technology Technical Council [doi]
• Organizing Committee [doi]
• Analytical Semi-Empirical Model for SER Sensitivity Estimation of Deep-Submicron CMOS CircuitsTino Heijmen. 3-8 [doi]
• Electrical Modeling for Laser Testing with Different Pulse DurationsA. Douin, V. Pouget, D. Lewis, Pascal Fouillat, Philippe Perdu. 9-13 [doi]
• Analyzing the Effectiveness of Fault Hardening ProceduresPiotr Gawkowski, Janusz Sosnowski, B. Radko. 14-19 [doi]
• On Transistor Level Gate Sizing for Increased Robustness to Transient FaultsJosé Manuel Cazeaux, Daniele Rossi, Martin Omaña, Cecilia Metra, Abhijit Chatterjee. 23-28 [doi]
• On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case StudyCristiano Lazzari, Lorena Anghel, Ricardo A. L. Reis. 29-34 [doi]
• Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS CircuitsYuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra. 35-40 [doi]
• Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault GradingCelia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes. 43-48 [doi]
• Heavy Ion Effects on Configuration Logic of Virtex FPGAsMonica Alderighi, A. Candelori, Fabio Casini, Sergio D Angelo, Marcello Mancini, Alessandro Paccagnella, Sandro Pastore, Giacomo R. Sechi. 49-53 [doi]
• Efficient Estimation of SEU Effects in SRAM-Based FPGAsMatteo Sonza Reorda, Luca Sterpone, Massimo Violante. 54-59 [doi]
• Impact of Soft Error Challenge on SoC DesignYervant Zorian, Valery A. Vardanian, K. Aleksanyan, K. Amirkhanyan. 63-68 [doi]
• DFT Assisted Built-In Soft Error ResilienceT. M. Mak, Subhasish Mitra, Ming Zhang. 69 [doi]
• Modeling Soft-Error Susceptibility for IP BlocksRobert C. Aitken, Betina Hold. 70-73 [doi]
• Trends and Trade-Offs in Designing Highly Robust Throughput Computing Oriented Chips and SystemsIshwar Parulkar, Robert Cypher. 74-77 [doi]
• Simulation and Mitigation of Single Event EffectsLorena Anghel, Michael Nicolaidis. 81 [doi]
• Use of Nuclear Codes for Neutron-Induced Nuclear Reactions in MicroelectronicsFrederic Wrobel. 82-86 [doi]
• A Review of DASIE Code Family: Contribution to SEU/MBU UnderstandingG. Hubert, N. Buard, C. Weulersse, T. Carriere, M.-C. Palau, J.-M. Palau, D. Lambert, J. Baggio, F. Wrobel, F. Saigne, R. Gaillard. 87-94 [doi]
• Design for Mitigation of Single Event EffectsMichael Nicolaidis. 95-96 [doi]
• Does It Mean Less Testing for Self Calibrating Design?T. M. Mak. 99 [doi]
• Self Calibrating Circuit Design for Variation Tolerant VLSI SystemsChris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy. 100-105 [doi]
• On-Chip Self-Calibration of RF Circuits Using Specification-Driven Built-In Self Test (S-BIST)Donghoon Han, Selim Sermet Akbay, Soumendu Bhattacharya, Abhijit Chatterjee, William R. Eisenstadt. 106-111 [doi]
• Introduction to the Special Session on Secure ImplementationsRégis Leveugle. 115 [doi]
• Introduction to Fault Attacks on SmartcardAntoine Lemarechal. 116 [doi]
• Security Constraints in Integrated CircuitsLaurent Sourgen. 117 [doi]
• Side-Channel Issues for Designing Secure Hardware ImplementationsLejla Batina, Nele Mentens, Ingrid Verbauwhede. 118-121 [doi]
• Security Testing for Hardware Products: The Security Evaluations PracticeAlain Merle, Jessy Clédière. 122-125 [doi]
• Hardening Techniques against Transient Faults for Asynchronous CircuitsYannick Monnet, Marc Renaudin, Régis Leveugle. 129-134 [doi]
• On-Line Testing of Globally Asynchronous CircuitsDelong Shang, Alexandre V. Bystrov, Alexandre Yakovlev, Deepali Koppad. 135-140 [doi]
• On-Line Error Detection and BIST for the AES Encryption Algorithm with Different S-Box ImplementationsVitalij Ocheretnij, G. Kouznetsov, Ramesh Karri, Michael Gössel. 141-146 [doi]
• Fast, Parallel Two-Rail Code Checker with Enhanced TestabilitySotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou. 149-156 [doi]
• Power-Balanced Self Checking Circuits for Cryptographic ChipsJulian Murphy, Alexandre V. Bystrov, Alexandre Yakovlev. 157-162 [doi]
• On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits Area Overhead and Performance OptimizationMartin Omaña, O. Losco, Cecilia Metra, Andrea Pagni. 163-168 [doi]
• Process Variation Tolerant Online Current Monitor for Robust SystemsQikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy. 171-176 [doi]
• A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI CircuitsB. Alorda, Sebastià A. Bota, Jaume Segura. 177-182 [doi]
• Coding Techniques for Low Switching Noise in Fault Tolerant BussesAndré K. Nieuwland, Atul Katoch, Daniele Rossi, Cecilia Metra. 183-189 [doi]
• Modeling of Transients Caused by a Laser Attack on Smart CardsDamien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache. 193-194 [doi]
• Scrubbing and Partitioning for Protection of Memory SystemsRiccardo Mariani, Gabriele Boschi. 195-196 [doi]
• A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded MemoryAndrzej Krasniewski. 197-198 [doi]
• A Software Based Online Memory Test for Highly Available SystemsAmandeep Singh, Debashish Bose. 199-200 [doi]
• Design of a Self Checking Reed Solomon EncoderGian-Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano. 201-202 [doi]
• Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan ShiftKentaroh Katoh, Abderrahim Doumar, Hideo Ito. 203-204 [doi]
• A 32-Bit COTS-Based Fault-Tolerant Embedded SystemAmir Rajabzadeh. 205-206 [doi]
• On the Proposition of an EMI-Based Fault Injection ApproachFabian Vargas, D. L. Cavalcante, E. Gatti, Dárcio Prestes, D. Lupi. 207-208 [doi]
• On-Line Testing for Secure Implementations: Design and ValidationRégis Leveugle, Yervant Zorian, Luca Breveglieri, André K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert. 211 [doi]
• Accumulator-Based Weighted Pattern GenerationIoannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis. 215-220 [doi]
• A Hamming Distance Based Test Pattern Generator with Improved Fault CoverageDhiraj K. Pradhan, Dimitri Kagaris, Rohit Gambhir. 221-226 [doi]
• Test Generation Methodology for High-Speed Floating Point AddersGeorge Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis. 227-232 [doi]
• Integrating BIST Techniques for On-Line SoC TestingAlberto Manzone, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Ernesto Sánchez, Matteo Sonza Reorda. 235-240 [doi]
• A Multi-Purpose Concept for SoC Self Test Including Diagnostic FeaturesRené Kothe, Christian Galke, Heinrich Theodor Vierhaus. 241-246 [doi]
• On the Need for Common Evaluation Methods for Fault Tolerance Costs in MicroprocessorsMichele Portolan, Régis Leveugle. 247-252 [doi]
• Increasing Fault Tolerance to Multiple Upsets Using Digital Sigma-Delta ModulatorsErik Schüler, Luigi Carro. 255-259 [doi]
• A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled MutationsRégis Leveugle. 260-265 [doi]
• Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAMBalkaran S. Gill, Michael Nicolaidis, Christos A. Papachristou. 266-271 [doi]
• Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm TechnologyAnimesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy. 275-280 [doi]
• Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD TestMarcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 281-286 [doi]
• A Novel On-Chip Delay Measurement Hardware for Efficient Speed-BinningArijit Raychowdhury, Swaroop Ghosh, Kaushik Roy. 287-292 [doi]
• Mitigating Soft Errors to Prevent a Hard Threat to Dependable ComputingYves Crouzet, Jacques Collet, Jean Arlat. 295-298 [doi]
• Overview of Soft Errors Issues in Aerospace SystemsChristian Boleat, Gerard Colas. 299-302 [doi]
• How to Characterize the Problem of SEU in Processors and Representative Errors Observed on FlightRaoul Velazco, R. Ecoffet, F. Faure. 303-308 [doi]
• Evaluation of SET and SEU Effects at Multiple Abstraction LevelsLorena Anghel, Régis Leveugle, Pierre Vanhauwaert. 309-312 [doi]
• How to Cope with SEU/SET at Chip Level? The Example of a Microprocessor FamilyNicolas Renaud. 313-314 [doi]
• How to Cope with SEU/SET at System Level?Michel Pignol. 315-318 [doi]
• Strategic Use of SEE Mitigation Techniques for the Development of the ESA Microprocessors: Past, Present and FutureAndre L. R. Pouponnot. 319-323 [doi]