Qing Dong, Zhehong Wang, Jongyup Lim, Yiqun Zhang 0002, Yi-Chun Shih, Yu-Der Chih, Jonathan Chang, David Blaauw, Dennis Sylvester. A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination. In 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018. pages 480-482, IEEE, 2018. [doi]
@inproceedings{DongWL0SCCBS18,
title = {A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination},
author = {Qing Dong and Zhehong Wang and Jongyup Lim and Yiqun Zhang 0002 and Yi-Chun Shih and Yu-Der Chih and Jonathan Chang and David Blaauw and Dennis Sylvester},
year = {2018},
doi = {10.1109/ISSCC.2018.8310393},
url = {https://doi.org/10.1109/ISSCC.2018.8310393},
researchr = {https://researchr.org/publication/DongWL0SCCBS18},
cites = {0},
citedby = {0},
pages = {480-482},
booktitle = {2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018},
publisher = {IEEE},
isbn = {978-1-5090-4940-0},
}