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Aristides Efthymiou, John Bainbridge, Douglas A. Edwards. Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. IEEE Trans. VLSI Syst., 13(12):1384-1393, 2005. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Adding Testability to an Asynchronous Interconnect for GALS SoCAristides Efthymiou, John Bainbridge, Douglas A. Edwards. ats 2004: 20-23 [doi] A Partial Scan Based Test Generation for Asynchronous CircuitsDilip P. Vasudevan, Aristides Efthymiou. ddecs 2008: 186-189 [doi]
The following publications are possibly variants of this publication: