The following publications are possibly variants of this publication:
- Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse FaultsT. Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piuri. dft 2003: 34 [doi]
- Reliability Modeling and Analysis of Clockless Wave Pipeline Core for Embedded Combinational Logic DesignTao Feng, Noh-Jin Park, Minsu Choi, Nohpill Park. tim, 59(7):1812-1824, 2010. [doi]
- Reliability Modeling and Assurance of Clockless Wave PipelineT. Feng, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi, Fred J. Meyer. dft 2004: 442-450 [doi]
- Automating Wave-Pipelined Circuit DesignWoo Jin Kim, Yong-Bin Kim. dt, 20(6):51-58, 2003. [doi]